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rocket-chip/fsim/Makefile

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Makefile
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#=======================================================================
# Makefile for Verilog simulation w/ VCS
#-----------------------------------------------------------------------
# Yunsup Lee (yunsup@cs.berkeley.edu)
#
# This makefile will build a rtl simulator and run various tests to
# verify proper functionality.
#
default: all
base_dir = $(abspath ..)
generated_dir = $(abspath ./generated-src)
mem_gen = $(base_dir)/fsim/fpga_mem_gen
sim_dir = .
output_dir = $(sim_dir)/output
BACKEND ?= fpga
CONFIG ?= DefaultFPGAConfig
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TB ?= rocketTestHarness
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include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag
-include $(generated_dir)/Makefrag-tests.$(CONFIG)
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include $(base_dir)/vsim/Makefrag-sim
all: $(simv)
debug: $(simv_debug)
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clean:
rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)
.PHONY: default all debug clean