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rocket-chip/rocket/src/main/scala/fpu.scala

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Scala
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package rocket
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import Chisel._
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import Node._
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import Constants._
import Instructions._
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object rocketFPConstants
{
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val FCMD_ADD = Bits("b000000")
val FCMD_SUB = Bits("b000001")
val FCMD_MUL = Bits("b000010")
val FCMD_DIV = Bits("b000011")
val FCMD_SQRT = Bits("b000100")
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val FCMD_SGNJ = Bits("b000101")
val FCMD_SGNJN = Bits("b000110")
val FCMD_SGNJX = Bits("b000111")
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val FCMD_CVT_L_FMT = Bits("b001000")
val FCMD_CVT_LU_FMT = Bits("b001001")
val FCMD_CVT_W_FMT = Bits("b001010")
val FCMD_CVT_WU_FMT = Bits("b001011")
val FCMD_CVT_FMT_L = Bits("b001100")
val FCMD_CVT_FMT_LU = Bits("b001101")
val FCMD_CVT_FMT_W = Bits("b001110")
val FCMD_CVT_FMT_WU = Bits("b001111")
val FCMD_CVT_FMT_S = Bits("b010000")
val FCMD_CVT_FMT_D = Bits("b010001")
val FCMD_EQ = Bits("b010101")
val FCMD_LT = Bits("b010110")
val FCMD_LE = Bits("b010111")
val FCMD_MIN = Bits("b011000")
val FCMD_MAX = Bits("b011001")
val FCMD_MFTX = Bits("b011100")
val FCMD_MFFSR = Bits("b011101")
val FCMD_MXTF = Bits("b011110")
val FCMD_MTFSR = Bits("b011111")
val FCMD_MADD = Bits("b100100")
val FCMD_MSUB = Bits("b100101")
val FCMD_NMSUB = Bits("b100110")
val FCMD_NMADD = Bits("b100111")
val FCMD_LOAD = Bits("b111000")
val FCMD_STORE = Bits("b111001")
val FCMD_WIDTH = 6
val FSR_WIDTH = 8
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}
import rocketFPConstants._
class rocketFPUCtrlSigs extends Bundle
{
val cmd = Bits(width = FCMD_WIDTH)
val valid = Bool()
val wen = Bool()
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val sboard = Bool()
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val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val single = Bool()
val fromint = Bool()
val toint = Bool()
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val fastpipe = Bool()
val fma = Bool()
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val store = Bool()
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val rdfsr = Bool()
val wrfsr = Bool()
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}
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class rocketFPUDecoder extends Component
{
val io = new Bundle {
val inst = Bits(32, INPUT)
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val sigs = new rocketFPUCtrlSigs().asOutput
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}
val N = Bool(false)
val Y = Bool(true)
val X = Bool(false)
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val FCMD_X = FCMD_ADD
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val decoder = ListLookup(io.inst,
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List (N,FCMD_X, X,X,X,X,X,X,X,X,X,X,X,X,X),
Array(FLW -> List(Y,FCMD_LOAD, Y,N,N,N,N,Y,N,N,N,N,N,N,N),
FLD -> List(Y,FCMD_LOAD, Y,N,N,N,N,N,N,N,N,N,N,N,N),
FSW -> List(Y,FCMD_STORE, N,N,N,Y,N,Y,N,N,N,N,Y,N,N),
FSD -> List(Y,FCMD_STORE, N,N,N,Y,N,N,N,N,N,N,Y,N,N),
MXTF_S -> List(Y,FCMD_MXTF, Y,N,N,N,N,Y,Y,N,Y,N,N,N,N),
MXTF_D -> List(Y,FCMD_MXTF, Y,N,N,N,N,N,Y,N,Y,N,N,N,N),
FCVT_S_W -> List(Y,FCMD_CVT_FMT_W, Y,N,N,N,N,Y,Y,N,Y,N,N,N,N),
FCVT_S_WU-> List(Y,FCMD_CVT_FMT_WU,Y,N,N,N,N,Y,Y,N,Y,N,N,N,N),
FCVT_S_L -> List(Y,FCMD_CVT_FMT_L, Y,N,N,N,N,Y,Y,N,Y,N,N,N,N),
FCVT_S_LU-> List(Y,FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,Y,N,Y,N,N,N,N),
FCVT_D_W -> List(Y,FCMD_CVT_FMT_W, Y,N,N,N,N,N,Y,N,Y,N,N,N,N),
FCVT_D_WU-> List(Y,FCMD_CVT_FMT_WU,Y,N,N,N,N,N,Y,N,Y,N,N,N,N),
FCVT_D_L -> List(Y,FCMD_CVT_FMT_L, Y,N,N,N,N,N,Y,N,Y,N,N,N,N),
FCVT_D_LU-> List(Y,FCMD_CVT_FMT_LU,Y,N,N,N,N,N,Y,N,Y,N,N,N,N),
MFTX_S -> List(Y,FCMD_MFTX, N,N,Y,N,N,Y,N,Y,N,N,N,N,N),
MFTX_D -> List(Y,FCMD_MFTX, N,N,Y,N,N,N,N,Y,N,N,N,N,N),
FCVT_W_S -> List(Y,FCMD_CVT_W_FMT, N,N,Y,N,N,Y,N,Y,N,N,N,N,N),
FCVT_WU_S-> List(Y,FCMD_CVT_WU_FMT,N,N,Y,N,N,Y,N,Y,N,N,N,N,N),
FCVT_L_S -> List(Y,FCMD_CVT_L_FMT, N,N,Y,N,N,Y,N,Y,N,N,N,N,N),
FCVT_LU_S-> List(Y,FCMD_CVT_LU_FMT,N,N,Y,N,N,Y,N,Y,N,N,N,N,N),
FCVT_W_D -> List(Y,FCMD_CVT_W_FMT, N,N,Y,N,N,N,N,Y,N,N,N,N,N),
FCVT_WU_D-> List(Y,FCMD_CVT_WU_FMT,N,N,Y,N,N,N,N,Y,N,N,N,N,N),
FCVT_L_D -> List(Y,FCMD_CVT_L_FMT, N,N,Y,N,N,N,N,Y,N,N,N,N,N),
FCVT_LU_D-> List(Y,FCMD_CVT_LU_FMT,N,N,Y,N,N,N,N,Y,N,N,N,N,N),
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FCVT_S_D -> List(Y,FCMD_CVT_FMT_D, Y,N,Y,N,N,Y,N,N,Y,N,N,N,N),
FCVT_D_S -> List(Y,FCMD_CVT_FMT_S, Y,N,Y,N,N,N,N,N,Y,N,N,N,N),
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FEQ_S -> List(Y,FCMD_EQ, N,N,Y,Y,N,Y,N,Y,N,N,N,N,N),
FLT_S -> List(Y,FCMD_LT, N,N,Y,Y,N,Y,N,Y,N,N,N,N,N),
FLE_S -> List(Y,FCMD_LE, N,N,Y,Y,N,Y,N,Y,N,N,N,N,N),
FEQ_D -> List(Y,FCMD_EQ, N,N,Y,Y,N,N,N,Y,N,N,N,N,N),
FLT_D -> List(Y,FCMD_LT, N,N,Y,Y,N,N,N,Y,N,N,N,N,N),
FLE_D -> List(Y,FCMD_LE, N,N,Y,Y,N,N,N,Y,N,N,N,N,N),
MTFSR -> List(Y,FCMD_MTFSR, N,N,N,N,N,Y,N,Y,N,N,N,Y,Y),
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MFFSR -> List(Y,FCMD_MFFSR, N,N,N,N,N,Y,N,Y,N,N,N,Y,N),
FSGNJ_S -> List(Y,FCMD_SGNJ, Y,N,Y,Y,N,Y,N,N,Y,N,N,N,N),
FSGNJN_S -> List(Y,FCMD_SGNJN, Y,N,Y,Y,N,Y,N,N,Y,N,N,N,N),
FSGNJX_S -> List(Y,FCMD_SGNJX, Y,N,Y,Y,N,Y,N,N,Y,N,N,N,N),
FSGNJ_D -> List(Y,FCMD_SGNJ, Y,N,Y,Y,N,N,N,N,Y,N,N,N,N),
FSGNJN_D -> List(Y,FCMD_SGNJN, Y,N,Y,Y,N,N,N,N,Y,N,N,N,N),
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FSGNJX_D -> List(Y,FCMD_SGNJX, Y,N,Y,Y,N,N,N,N,Y,N,N,N,N),
FMIN_S -> List(Y,FCMD_MIN, Y,N,Y,Y,N,Y,N,N,Y,N,N,N,N),
FMAX_S -> List(Y,FCMD_MAX, Y,N,Y,Y,N,Y,N,N,Y,N,N,N,N),
FMIN_D -> List(Y,FCMD_MIN, Y,N,Y,Y,N,N,N,N,Y,N,N,N,N),
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FMAX_D -> List(Y,FCMD_MAX, Y,N,Y,Y,N,N,N,N,Y,N,N,N,N),
FADD_S -> List(Y,FCMD_ADD, Y,Y,Y,Y,N,Y,N,N,N,Y,N,N,N),
FSUB_S -> List(Y,FCMD_SUB, Y,Y,Y,Y,N,Y,N,N,N,Y,N,N,N),
FMUL_S -> List(Y,FCMD_MUL, Y,Y,Y,Y,N,Y,N,N,N,Y,N,N,N),
FADD_D -> List(Y,FCMD_ADD, Y,Y,Y,Y,N,N,N,N,N,Y,N,N,N),
FSUB_D -> List(Y,FCMD_SUB, Y,Y,Y,Y,N,N,N,N,N,Y,N,N,N),
FMUL_D -> List(Y,FCMD_MUL, Y,Y,Y,Y,N,N,N,N,N,Y,N,N,N),
FMADD_S -> List(Y,FCMD_MADD, Y,Y,Y,Y,Y,Y,N,N,N,Y,N,N,N),
FMSUB_S -> List(Y,FCMD_MSUB, Y,Y,Y,Y,Y,Y,N,N,N,Y,N,N,N),
FNMADD_S -> List(Y,FCMD_NMADD, Y,Y,Y,Y,Y,Y,N,N,N,Y,N,N,N),
FNMSUB_S -> List(Y,FCMD_NMSUB, Y,Y,Y,Y,Y,Y,N,N,N,Y,N,N,N),
FMADD_D -> List(Y,FCMD_MADD, Y,Y,Y,Y,Y,N,N,N,N,Y,N,N,N),
FMSUB_D -> List(Y,FCMD_MSUB, Y,Y,Y,Y,Y,N,N,N,N,Y,N,N,N),
FNMADD_D -> List(Y,FCMD_NMADD, Y,Y,Y,Y,Y,N,N,N,N,Y,N,N,N),
FNMSUB_D -> List(Y,FCMD_NMSUB, Y,Y,Y,Y,Y,N,N,N,N,Y,N,N,N)
))
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val valid :: cmd :: wen :: sboard :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: fastpipe :: fma :: store :: rdfsr :: wrfsr :: Nil = decoder
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io.sigs.valid := valid.toBool
io.sigs.cmd := cmd
io.sigs.wen := wen.toBool
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io.sigs.sboard := sboard.toBool
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io.sigs.ren1 := ren1.toBool
io.sigs.ren2 := ren2.toBool
io.sigs.ren3 := ren3.toBool
io.sigs.single := single.toBool
io.sigs.fromint := fromint.toBool
io.sigs.toint := toint.toBool
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io.sigs.fastpipe := fastpipe.toBool
io.sigs.fma := fma.toBool
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io.sigs.store := store.toBool
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io.sigs.rdfsr := rdfsr.toBool
io.sigs.wrfsr := wrfsr.toBool
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}
class ioDpathFPU extends Bundle {
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val inst = Bits(32, OUTPUT)
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val fromint_data = Bits(64, OUTPUT)
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val store_data = Bits(64, INPUT)
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val toint_data = Bits(64, INPUT)
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val dmem_resp_val = Bool(OUTPUT)
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val dmem_resp_type = Bits(3, OUTPUT)
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val dmem_resp_tag = UFix(5, OUTPUT)
val dmem_resp_data = Bits(64, OUTPUT)
}
class ioCtrlFPU extends Bundle {
val valid = Bool(OUTPUT)
val nack = Bool(INPUT)
val illegal_rm = Bool(INPUT)
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val killx = Bool(OUTPUT)
val killm = Bool(OUTPUT)
val dec = new rocketFPUCtrlSigs().asInput
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val sboard_clr = Bool(INPUT)
val sboard_clra = UFix(5, INPUT)
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}
class rocketFPIntUnit extends Component
{
val io = new Bundle {
val single = Bool(INPUT)
val cmd = Bits(FCMD_WIDTH, INPUT)
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val rm = Bits(3, INPUT)
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val fsr = Bits(FSR_WIDTH, INPUT)
val in1 = Bits(65, INPUT)
val in2 = Bits(65, INPUT)
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val lt_s = Bool(OUTPUT)
val lt_d = Bool(OUTPUT)
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val store_data = Bits(64, OUTPUT)
val toint_data = Bits(64, OUTPUT)
val exc = Bits(5, OUTPUT)
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}
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val unrec_s = new hardfloat.recodedFloat32ToFloat32
val unrec_d = new hardfloat.recodedFloat64ToFloat64
unrec_s.io.in := io.in1
unrec_d.io.in := io.in1
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io.store_data := Mux(io.single, Cat(unrec_s.io.out, unrec_s.io.out), unrec_d.io.out)
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val scmp = new hardfloat.recodedFloat32Compare
scmp.io.a := io.in1
scmp.io.b := io.in2
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val scmp_out = (io.cmd & Cat(scmp.io.a_lt_b, scmp.io.a_eq_b)).orR
val scmp_exc = (io.cmd & Cat(scmp.io.a_lt_b_invalid, scmp.io.a_eq_b_invalid)).orR << UFix(4)
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val s2i = new hardfloat.recodedFloat32ToAny
s2i.io.in := io.in1
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s2i.io.roundingMode := io.rm
s2i.io.typeOp := ~io.cmd(1,0)
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val dcmp = new hardfloat.recodedFloat64Compare
dcmp.io.a := io.in1
dcmp.io.b := io.in2
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val dcmp_out = (io.cmd & Cat(dcmp.io.a_lt_b, dcmp.io.a_eq_b)).orR
val dcmp_exc = (io.cmd & Cat(dcmp.io.a_lt_b_invalid, dcmp.io.a_eq_b_invalid)).orR << UFix(4)
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val d2i = new hardfloat.recodedFloat64ToAny
d2i.io.in := io.in1
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d2i.io.roundingMode := io.rm
d2i.io.typeOp := ~io.cmd(1,0)
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// output muxing
val (out_s, exc_s) = (Wire() { Bits() }, Wire() { Bits() })
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out_s := Cat(Fill(32, unrec_s.io.out(31)), unrec_s.io.out)
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exc_s := Bits(0)
val (out_d, exc_d) = (Wire() { Bits() }, Wire() { Bits() })
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out_d := unrec_d.io.out
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exc_d := Bits(0)
when (io.cmd === FCMD_MTFSR || io.cmd === FCMD_MFFSR) {
out_s := io.fsr
}
when (io.cmd === FCMD_CVT_W_FMT || io.cmd === FCMD_CVT_WU_FMT) {
out_s := Cat(Fill(32, s2i.io.out(31)), s2i.io.out(31,0))
exc_s := s2i.io.exceptionFlags
out_d := Cat(Fill(32, d2i.io.out(31)), d2i.io.out(31,0))
exc_d := d2i.io.exceptionFlags
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}
when (io.cmd === FCMD_CVT_L_FMT || io.cmd === FCMD_CVT_LU_FMT) {
out_s := s2i.io.out
exc_s := s2i.io.exceptionFlags
out_d := d2i.io.out
exc_d := d2i.io.exceptionFlags
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}
when (io.cmd === FCMD_EQ || io.cmd === FCMD_LT || io.cmd === FCMD_LE) {
out_s := scmp_out
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exc_s := scmp_exc
out_d := dcmp_out
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exc_d := dcmp_exc
}
io.toint_data := Mux(io.single, out_s, out_d)
io.exc := Mux(io.single, exc_s, exc_d)
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io.lt_s := scmp.io.a_lt_b
io.lt_d := dcmp.io.a_lt_b
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}
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class rocketFPUFastPipe extends Component
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{
val io = new Bundle {
val single = Bool(INPUT)
val cmd = Bits(FCMD_WIDTH, INPUT)
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val rm = Bits(3, INPUT)
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val fromint = Bits(64, INPUT)
val in1 = Bits(65, INPUT)
val in2 = Bits(65, INPUT)
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val lt_s = Bool(INPUT)
val lt_d = Bool(INPUT)
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val out_s = Bits(33, OUTPUT)
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val exc_s = Bits(5, OUTPUT)
val out_d = Bits(65, OUTPUT)
val exc_d = Bits(5, OUTPUT)
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}
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// int->fp units
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val rec_s = new hardfloat.float32ToRecodedFloat32
val rec_d = new hardfloat.float64ToRecodedFloat64
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rec_s.io.in := io.fromint
rec_d.io.in := io.fromint
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val i2s = new hardfloat.anyToRecodedFloat32
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i2s.io.in := io.fromint
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i2s.io.roundingMode := io.rm
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i2s.io.typeOp := ~io.cmd(1,0)
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val i2d = new hardfloat.anyToRecodedFloat64
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i2d.io.in := io.fromint
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i2d.io.roundingMode := io.rm
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i2d.io.typeOp := ~io.cmd(1,0)
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// fp->fp units
val sign_s = Mux(io.cmd === FCMD_SGNJ, io.in2(32),
Mux(io.cmd === FCMD_SGNJN, ~io.in2(32),
io.in1(32) ^ io.in2(32))) // FCMD_SGNJX
val sign_d = Mux(io.cmd === FCMD_SGNJ, io.in2(64),
Mux(io.cmd === FCMD_SGNJN, ~io.in2(64),
io.in1(64) ^ io.in2(64))) // FCMD_SGNJX
val fsgnj = Cat(Mux(io.single, io.in1(64), sign_d), io.in1(63,33),
Mux(io.single, sign_s, io.in1(32)), io.in1(31,0))
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val s2d = new hardfloat.recodedFloat32ToRecodedFloat64
s2d.io.in := io.in1
val d2s = new hardfloat.recodedFloat64ToRecodedFloat32
d2s.io.in := io.in1
d2s.io.roundingMode := io.rm
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val isnan1 = Mux(io.single, io.in1(31,29) === Bits("b111"), io.in1(63,61) === Bits("b111"))
val isnan2 = Mux(io.single, io.in2(31,29) === Bits("b111"), io.in2(63,61) === Bits("b111"))
val issnan1 = isnan1 && ~Mux(io.single, io.in1(22), io.in1(51))
val issnan2 = isnan2 && ~Mux(io.single, io.in2(22), io.in2(51))
val minmax_exc = Cat(issnan1 || issnan2, Bits(0,4))
val min = io.cmd === FCMD_MIN
val lt = Mux(io.single, io.lt_s, io.lt_d)
val minmax = Mux(isnan2 || !isnan1 && (min === lt), io.in1, io.in2)
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// output muxing
val (out_s, exc_s) = (Wire() { Bits() }, Wire() { Bits() })
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out_s := Reg(rec_s.io.out)
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exc_s := Bits(0)
val (out_d, exc_d) = (Wire() { Bits() }, Wire() { Bits() })
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out_d := Reg(rec_d.io.out)
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exc_d := Bits(0)
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val r_cmd = Reg(io.cmd)
when (r_cmd === FCMD_MTFSR || r_cmd === FCMD_MFFSR) {
out_s := Reg(io.fromint(FSR_WIDTH-1,0))
}
when (r_cmd === FCMD_SGNJ || r_cmd === FCMD_SGNJN || r_cmd === FCMD_SGNJX) {
val r_fsgnj = Reg(fsgnj)
out_s := r_fsgnj(32,0)
out_d := r_fsgnj
}
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when (r_cmd === FCMD_MIN || r_cmd === FCMD_MAX) {
val r_minmax = Reg(minmax)
val r_minmax_exc = Reg(minmax_exc)
out_s := r_minmax(32,0)
out_d := r_minmax
exc_s := r_minmax_exc
exc_d := r_minmax_exc
}
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when (r_cmd === FCMD_CVT_FMT_S || r_cmd === FCMD_CVT_FMT_D) {
out_s := Reg(d2s.io.out)
exc_s := Reg(d2s.io.exceptionFlags)
out_d := Reg(s2d.io.out)
exc_d := Reg(s2d.io.exceptionFlags)
}
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when (r_cmd === FCMD_CVT_FMT_W || r_cmd === FCMD_CVT_FMT_WU ||
r_cmd === FCMD_CVT_FMT_L || r_cmd === FCMD_CVT_FMT_LU) {
out_s := Reg(i2s.io.out)
exc_s := Reg(i2s.io.exceptionFlags)
out_d := Reg(i2d.io.out)
exc_d := Reg(i2d.io.exceptionFlags)
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}
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io.out_s := out_s
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io.exc_s := exc_s
io.out_d := out_d
io.exc_d := exc_d
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}
class ioFMA(width: Int) extends Bundle {
val valid = Bool(INPUT)
val cmd = Bits(FCMD_WIDTH, INPUT)
val rm = Bits(3, INPUT)
val in1 = Bits(width, INPUT)
val in2 = Bits(width, INPUT)
val in3 = Bits(width, INPUT)
val out = Bits(width, OUTPUT)
val exc = Bits(5, OUTPUT)
}
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class rocketFPUSFMAPipe(latency: Int) extends Component
{
val io = new ioFMA(33)
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val cmd = Reg() { Bits() }
val rm = Reg() { Bits() }
val in1 = Reg() { Bits() }
val in2 = Reg() { Bits() }
val in3 = Reg() { Bits() }
val cmd_fma = io.cmd === FCMD_MADD || io.cmd === FCMD_MSUB ||
io.cmd === FCMD_NMADD || io.cmd === FCMD_NMSUB
val cmd_addsub = io.cmd === FCMD_ADD || io.cmd === FCMD_SUB
val one = Bits("h80000000")
val zero = Cat(io.in1(32) ^ io.in2(32), Bits(0, 32))
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when (io.valid) {
cmd := Cat(io.cmd(1) & (cmd_fma || cmd_addsub), io.cmd(0))
rm := io.rm
in1 := io.in1
in2 := Mux(cmd_addsub, one, io.in2)
in3 := Mux(cmd_fma, io.in3, Mux(cmd_addsub, io.in2, zero))
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}
val fma = new hardfloat.mulAddSubRecodedFloat32_1
fma.io.op := cmd
fma.io.roundingMode := rm
fma.io.a := in1
fma.io.b := in2
fma.io.c := in3
io.out := ShiftRegister(latency-1, fma.io.out)
io.exc := ShiftRegister(latency-1, fma.io.exceptionFlags)
}
class rocketFPUDFMAPipe(latency: Int) extends Component
{
val io = new ioFMA(65)
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val cmd = Reg() { Bits() }
val rm = Reg() { Bits() }
val in1 = Reg() { Bits() }
val in2 = Reg() { Bits() }
val in3 = Reg() { Bits() }
val cmd_fma = io.cmd === FCMD_MADD || io.cmd === FCMD_MSUB ||
io.cmd === FCMD_NMADD || io.cmd === FCMD_NMSUB
val cmd_addsub = io.cmd === FCMD_ADD || io.cmd === FCMD_SUB
val one = Bits("h8000000000000000")
val zero = Cat(io.in1(64) ^ io.in2(64), Bits(0, 64))
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when (io.valid) {
cmd := Cat(io.cmd(1) & (cmd_fma || cmd_addsub), io.cmd(0))
rm := io.rm
in1 := io.in1
in2 := Mux(cmd_addsub, one, io.in2)
in3 := Mux(cmd_fma, io.in3, Mux(cmd_addsub, io.in2, zero))
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}
val fma = new hardfloat.mulAddSubRecodedFloat64_1
fma.io.op := cmd
fma.io.roundingMode := rm
fma.io.a := in1
fma.io.b := in2
fma.io.c := in3
io.out := ShiftRegister(latency-1, fma.io.out)
io.exc := ShiftRegister(latency-1, fma.io.exceptionFlags)
}
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class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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{
val io = new Bundle {
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val ctrl = new ioCtrlFPU().flip
val dpath = new ioDpathFPU().flip
val sfma = new ioFMA(33)
val dfma = new ioFMA(65)
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}
val ex_reg_inst = Reg() { Bits() }
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when (io.ctrl.valid) {
ex_reg_inst := io.dpath.inst
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}
val ex_reg_valid = Reg(io.ctrl.valid, Bool(false))
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val fp_decoder = new rocketFPUDecoder
fp_decoder.io.inst := io.dpath.inst
val ctrl = Reg() { new rocketFPUCtrlSigs }
when (io.ctrl.valid) {
ctrl := fp_decoder.io.sigs
}
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val mem_ctrl = Reg(ctrl)
val wb_ctrl = Reg(mem_ctrl)
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// load response
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val load_wb = Reg(io.dpath.dmem_resp_val, resetVal = Bool(false))
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val load_wb_single = Reg() { Bool() }
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val load_wb_data = Reg() { Bits(width = 64) } // XXX WTF why doesn't bit width inference work for the regfile?!
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val load_wb_tag = Reg() { UFix() }
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when (io.dpath.dmem_resp_val) {
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load_wb_single := io.dpath.dmem_resp_type === MT_W || io.dpath.dmem_resp_type === MT_WU
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load_wb_data := io.dpath.dmem_resp_data
load_wb_tag := io.dpath.dmem_resp_tag
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}
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val rec_s = new hardfloat.float32ToRecodedFloat32
val rec_d = new hardfloat.float64ToRecodedFloat64
rec_s.io.in := load_wb_data
rec_d.io.in := load_wb_data
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val sp_msbs = Fill(32, UFix(1,1))
val load_wb_data_recoded = Mux(load_wb_single, Cat(sp_msbs, rec_s.io.out), rec_d.io.out)
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val fsr_rm = Reg() { Bits(width = 3) }
val fsr_exc = Reg() { Bits(width = 5) }
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// regfile
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val regfile = Mem(32, load_wb, load_wb_tag, load_wb_data_recoded);
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regfile.setReadLatency(0);
regfile.setTarget('inst);
val ex_rs1 = regfile.read(ex_reg_inst(26,22))
val ex_rs2 = regfile.read(ex_reg_inst(21,17))
val ex_rs3 = regfile.read(ex_reg_inst(16,12))
val ex_rm = Mux(ex_reg_inst(11,9) === Bits(7), fsr_rm, ex_reg_inst(11,9))
val mem_reg_valid = Reg(ex_reg_valid && !io.ctrl.killx, resetVal = Bool(false))
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val mem_fromint_data = Reg() { Bits() }
val mem_rs1 = Reg() { Bits() }
val mem_rs2 = Reg() { Bits() }
val mem_rs3 = Reg() { Bits() }
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val mem_rm = Reg() { Bits() }
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when (ex_reg_valid) {
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mem_rm := ex_rm
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when (ctrl.fromint || ctrl.wrfsr) {
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mem_fromint_data := io.dpath.fromint_data
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}
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when (ctrl.ren1) {
mem_rs1 := ex_rs1
}
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when (ctrl.store) {
mem_rs1 := ex_rs2
}
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when (ctrl.ren2) {
mem_rs2 := ex_rs2
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}
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when (ctrl.ren3) {
mem_rs3 := ex_rs3
}
}
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// currently we assume FP stores and FP->int ops take 1 cycle (MEM)
val fpiu = new rocketFPIntUnit
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fpiu.io.single := mem_ctrl.single
fpiu.io.cmd := mem_ctrl.cmd
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fpiu.io.rm := mem_rm
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fpiu.io.fsr := Cat(fsr_rm, fsr_exc)
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fpiu.io.in1 := mem_rs1
fpiu.io.in2 := mem_rs2
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io.dpath.store_data := fpiu.io.store_data
io.dpath.toint_data := fpiu.io.toint_data
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// 2-cycle pipe for int->FP and non-FMA FP->FP ops
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val fastpipe = new rocketFPUFastPipe
fastpipe.io.single := mem_ctrl.single
fastpipe.io.cmd := mem_ctrl.cmd
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fastpipe.io.rm := mem_rm
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fastpipe.io.fromint := mem_fromint_data
fastpipe.io.in1 := mem_rs1
fastpipe.io.in2 := mem_rs2
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fastpipe.io.lt_s := fpiu.io.lt_s
fastpipe.io.lt_d := fpiu.io.lt_d
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val cmd_fma = mem_ctrl.cmd === FCMD_MADD || mem_ctrl.cmd === FCMD_MSUB ||
mem_ctrl.cmd === FCMD_NMADD || mem_ctrl.cmd === FCMD_NMSUB
val cmd_addsub = mem_ctrl.cmd === FCMD_ADD || mem_ctrl.cmd === FCMD_SUB
val sfma = new rocketFPUSFMAPipe(sfma_latency-1)
sfma.io.valid := io.sfma.valid || mem_reg_valid && mem_ctrl.fma && mem_ctrl.single
sfma.io.in1 := Mux(io.sfma.valid, io.sfma.in1, mem_rs1)
sfma.io.in2 := Mux(io.sfma.valid, io.sfma.in2, mem_rs2)
sfma.io.in3 := Mux(io.sfma.valid, io.sfma.in3, mem_rs3)
sfma.io.cmd := Mux(io.sfma.valid, io.sfma.cmd, mem_ctrl.cmd)
sfma.io.rm := Mux(io.sfma.valid, io.sfma.rm, mem_rm)
io.sfma.out := sfma.io.out
io.sfma.exc := sfma.io.exc
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val dfma = new rocketFPUDFMAPipe(dfma_latency-1)
dfma.io.valid := io.dfma.valid || mem_reg_valid && mem_ctrl.fma && !mem_ctrl.single
dfma.io.in1 := Mux(io.dfma.valid, io.dfma.in1, mem_rs1)
dfma.io.in2 := Mux(io.dfma.valid, io.dfma.in2, mem_rs2)
dfma.io.in3 := Mux(io.dfma.valid, io.dfma.in3, mem_rs3)
dfma.io.cmd := Mux(io.dfma.valid, io.dfma.cmd, mem_ctrl.cmd)
dfma.io.rm := Mux(io.dfma.valid, io.dfma.rm, mem_rm)
io.dfma.out := dfma.io.out
io.dfma.exc := dfma.io.exc
val wb_reg_valid = Reg(mem_reg_valid && !io.ctrl.killm, resetVal = Bool(false))
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val wb_toint_exc = Reg(fpiu.io.exc)
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// writeback arbitration
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val wen = Reg(resetVal = Bits(0, dfma_latency))
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val winfo = Vec(dfma_latency-1) { Reg() { Bits() } }
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val mem_wen = Reg(resetVal = Bool(false))
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val fastpipe_latency = 2
require(fastpipe_latency < sfma_latency && sfma_latency <= dfma_latency)
val ex_stage_fu_latency = Mux(ctrl.fastpipe, UFix(fastpipe_latency-1),
Mux(ctrl.single, UFix(sfma_latency-1),
UFix(dfma_latency-1)))
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val mem_fu_latency = Reg(ex_stage_fu_latency - UFix(1))
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val write_port_busy = ctrl.fastpipe && wen(fastpipe_latency) ||
Bool(sfma_latency < dfma_latency) && ctrl.fma && ctrl.single && wen(sfma_latency) ||
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mem_wen && mem_fu_latency === ex_stage_fu_latency
mem_wen := ex_reg_valid && !io.ctrl.killx && (ctrl.fma || ctrl.fastpipe)
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val ex_stage_wsrc = Cat(ctrl.fastpipe, ctrl.single)
val mem_winfo = Reg(Cat(ex_reg_inst(31,27), ex_stage_wsrc))
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for (i <- 0 until dfma_latency-2) {
winfo(i) := winfo(i+1)
}
wen := wen >> UFix(1)
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when (mem_wen) {
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when (!io.ctrl.killm) {
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wen := (wen >> UFix(1)) | (UFix(1) << mem_fu_latency)
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}
for (i <- 0 until dfma_latency-1) {
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when (UFix(i) === mem_fu_latency) {
winfo(i) := mem_winfo
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}
}
}
val wsrc = winfo(0)(1,0)
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val wdata = Mux(wsrc === UFix(0), dfma.io.out, // DFMA
Mux(wsrc === UFix(1), Cat(sp_msbs, sfma.io.out), // SFMA
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Mux(wsrc === UFix(2), fastpipe.io.out_d,
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Cat(sp_msbs, fastpipe.io.out_s))))
val wexc = Mux(wsrc === UFix(0), dfma.io.exc, // DFMA
Mux(wsrc === UFix(1), sfma.io.exc, // SFMA
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Mux(wsrc === UFix(2), fastpipe.io.exc_d,
fastpipe.io.exc_s)))
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val waddr = winfo(0).toUFix >> UFix(2)
regfile.write(waddr(4,0), wdata, wen(0))
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when (wb_reg_valid && wb_ctrl.toint || wen(0)) {
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fsr_exc := fsr_exc |
Fill(fsr_exc.getWidth, wb_reg_valid && wb_ctrl.toint) & wb_toint_exc |
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Fill(fsr_exc.getWidth, wen(0)) & wexc
}
when (wb_reg_valid && wb_ctrl.wrfsr) {
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fsr_exc := fastpipe.io.out_s(4,0)
fsr_rm := fastpipe.io.out_s(7,5)
}
val fp_inflight = mem_reg_valid && mem_ctrl.toint || wb_reg_valid && wb_ctrl.toint || mem_wen || wen.orR
val fsr_busy = ctrl.rdfsr && fp_inflight || mem_reg_valid && mem_ctrl.wrfsr || wb_reg_valid && wb_ctrl.wrfsr
val units_busy = mem_reg_valid && mem_ctrl.fma && (io.sfma.valid && mem_ctrl.single || io.dfma.valid && !mem_ctrl.single)
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io.ctrl.nack := fsr_busy || units_busy || write_port_busy
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io.ctrl.dec <> fp_decoder.io.sigs
// we don't currently support round-max-magnitude (rm=4)
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io.ctrl.illegal_rm := ex_rm(2)
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io.ctrl.sboard_clr := wen(0) && !wsrc(1).toBool // only for FMA pipes
io.ctrl.sboard_clra := waddr
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}