2011-11-09 23:52:17 +01:00
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package Top
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{
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import Chisel._;
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import Node._;
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import Constants._;
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import scala.math._;
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2011-11-10 20:26:13 +01:00
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class ioCAM(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle {
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val clear = Bool('input);
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2011-11-09 23:52:17 +01:00
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val tag = Bits(tag_bits, 'input);
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val hit = Bool('output);
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val hit_addr = UFix(addr_bits, 'output);
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2011-11-10 20:26:13 +01:00
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val valid_bits = Bits(entries, 'output);
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2011-11-09 23:52:17 +01:00
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val write = Bool('input);
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val write_tag = Bits(tag_bits, 'input);
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val write_addr = UFix(addr_bits, 'input);
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}
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class rocketCAM(entries: Int, addr_bits: Int, tag_bits: Int) extends Component {
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2011-11-10 20:26:13 +01:00
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val io = new ioCAM(entries, addr_bits, tag_bits);
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val cam_tags = Mem(entries, io.write, io.write_addr, io.write_tag);
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2011-11-09 23:52:17 +01:00
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2011-11-10 20:26:13 +01:00
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val l_hit = Wire() { Bool() };
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val l_hit_addr = Wire() { UFix() };
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2011-11-09 23:52:17 +01:00
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2011-11-10 20:26:13 +01:00
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val vb_array = Reg(resetVal = Bits(0, entries));
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when (io.clear) {
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vb_array <== Bits(0, entries);
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}
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when (io.write) {
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vb_array <== vb_array.bitSet(io.write_addr, Bool(true));
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}
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2011-11-09 23:52:17 +01:00
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2011-11-10 20:26:13 +01:00
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for (i <- 0 to entries-1) {
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when (vb_array(UFix(i)).toBool && (cam_tags(UFix(i)) === io.tag)) {
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l_hit <== Bool(true);
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l_hit_addr <== UFix(i,addr_bits);
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}
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}
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l_hit <== Bool(false);
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l_hit_addr <== UFix(0, addr_bits);
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io.valid_bits := vb_array;
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io.hit := l_hit;
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io.hit_addr := l_hit_addr;
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2011-11-09 23:52:17 +01:00
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}
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// interface between TLB and PTW
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class ioTLB_PTW extends Bundle
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{
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// requests
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val req_val = Bool('output);
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val req_rdy = Bool('input);
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val req_vpn = Bits(VPN_BITS, 'output);
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// responses
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val resp_val = Bool('input);
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val resp_err = Bool('input);
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val resp_ppn = Bits(PPN_BITS, 'input);
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val resp_perm = Bits(PERM_BITS, 'input);
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}
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// interface between ITLB and fetch stage of pipeline
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2011-11-10 06:54:11 +01:00
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class ioITLB_CPU(view: List[String] = null) extends Bundle(view)
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2011-11-09 23:52:17 +01:00
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{
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// status bits (from PCR), to check current permission and whether VM is enabled
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val status = Bits(17, 'input);
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// invalidate all TLB entries
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val invalidate = Bool('input);
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// lookup requests
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val req_val = Bool('input);
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val req_rdy = Bool('output);
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val req_asid = Bits(ASID_BITS, 'input);
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2011-11-12 03:48:34 +01:00
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val req_vpn = UFix(VPN_BITS, 'input);
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2011-11-09 23:52:17 +01:00
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// lookup responses
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2011-11-12 03:48:34 +01:00
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val resp_miss = Bool('output);
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// val resp_val = Bool('output);
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val resp_ppn = UFix(PPN_BITS, 'output);
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2011-11-09 23:52:17 +01:00
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val exception = Bool('output);
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}
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class ioITLB extends Bundle
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{
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val cpu = new ioITLB_CPU();
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val ptw = new ioTLB_PTW();
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}
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class rocketITLB(entries: Int) extends Component
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{
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val addr_bits = ceil(log10(entries)/log10(2)).toInt;
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val io = new ioITLB();
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val s_ready :: s_request :: s_wait :: Nil = Enum(3) { UFix() };
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val state = Reg(resetVal = s_ready);
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2011-11-12 03:48:34 +01:00
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val r_cpu_req_vpn = Reg(resetVal = Bits(0, VPN_BITS));
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val r_cpu_req_val = Reg(resetVal = Bool(false));
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val r_cpu_req_asid = Reg(resetVal = Bits(0,ASID_BITS));
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2011-11-09 23:52:17 +01:00
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val r_refill_tag = Reg(resetVal = Bits(0, ASID_BITS+VPN_BITS));
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val r_refill_waddr = Reg(resetVal = UFix(0, addr_bits));
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val repl_count = Reg(resetVal = UFix(0, addr_bits));
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2011-11-12 03:48:34 +01:00
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when (io.cpu.req_val && io.cpu.req_rdy) {
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r_cpu_req_vpn <== io.cpu.req_vpn;
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r_cpu_req_asid <== io.cpu.req_asid;
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}
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when (io.cpu.req_rdy) {
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r_cpu_req_val <== io.cpu.req_val;
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}
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val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn);
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val tag_cam = new rocketCAM(entries, addr_bits, ASID_BITS+VPN_BITS);
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2011-11-09 23:52:17 +01:00
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val tag_ram = Mem(entries, io.ptw.resp_val, r_refill_waddr.toUFix, io.ptw.resp_ppn);
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2011-11-10 20:26:13 +01:00
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tag_cam.io.clear := io.cpu.invalidate;
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2011-11-09 23:52:17 +01:00
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tag_cam.io.tag := lookup_tag;
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2011-11-13 00:47:47 +01:00
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tag_cam.io.write := io.ptw.resp_val || io.ptw.resp_err;
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2011-11-09 23:52:17 +01:00
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tag_cam.io.write_tag := r_refill_tag;
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tag_cam.io.write_addr := r_refill_waddr;
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2011-11-12 03:48:34 +01:00
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val tag_hit = tag_cam.io.hit;
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val tag_hit_addr = tag_cam.io.hit_addr;
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2011-11-09 23:52:17 +01:00
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// extract fields from status register
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2011-11-11 02:41:22 +01:00
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val status_s = io.cpu.status(SR_S).toBool; // user/supervisor mode
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val status_u = !status_s;
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val status_vm = io.cpu.status(SR_VM).toBool // virtual memory enable
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2011-11-09 23:52:17 +01:00
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// extract fields from PT permission bits
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2011-11-10 06:54:11 +01:00
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val ptw_perm_ux = io.ptw.resp_perm(0);
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val ptw_perm_sx = io.ptw.resp_perm(3);
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2011-11-09 23:52:17 +01:00
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// permission bit arrays
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val ux_array = Reg(resetVal = Bits(0, entries)); // user execute permission
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val sx_array = Reg(resetVal = Bits(0, entries)); // supervisor execute permission
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when (io.ptw.resp_val) {
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ux_array <== ux_array.bitSet(r_refill_waddr, ptw_perm_ux);
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2011-11-10 06:54:11 +01:00
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sx_array <== sx_array.bitSet(r_refill_waddr, ptw_perm_sx);
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}
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// when the page table lookup reports an error, set both execute permission
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// bits to 0 so the next access will cause an exceptions
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when (io.ptw.resp_err) {
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ux_array <== ux_array.bitSet(r_refill_waddr, Bool(false));
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sx_array <== sx_array.bitSet(r_refill_waddr, Bool(false));
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2011-11-09 23:52:17 +01:00
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}
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2011-11-10 20:26:13 +01:00
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// high if there are any unused entries in the ITLB
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val invalid_entry = (tag_cam.io.valid_bits != ~Bits(0,entries));
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2011-11-09 23:52:17 +01:00
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val ie_enc = new priorityEncoder(entries);
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2011-11-10 20:26:13 +01:00
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ie_enc.io.in := ~tag_cam.io.valid_bits.toUFix;
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2011-11-09 23:52:17 +01:00
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val ie_addr = ie_enc.io.out;
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val repl_waddr = Mux(invalid_entry, ie_addr, repl_count).toUFix;
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2011-11-13 08:39:43 +01:00
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val lookup = (state === s_ready) && r_cpu_req_val;
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val lookup_hit = lookup && tag_hit;
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val lookup_miss = lookup && !tag_hit;
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2011-11-11 02:41:22 +01:00
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val tlb_hit = status_vm && lookup_hit;
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val tlb_miss = status_vm && lookup_miss;
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2011-11-09 23:52:17 +01:00
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2011-11-11 02:41:22 +01:00
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when (tlb_miss) {
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2011-11-09 23:52:17 +01:00
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r_refill_tag <== lookup_tag;
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r_refill_waddr <== repl_waddr;
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when (!invalid_entry) {
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repl_count <== repl_count + UFix(1);
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}
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}
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2011-11-13 08:39:43 +01:00
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// exception check
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val outofrange = (io.cpu.resp_ppn > UFix(MEMSIZE_PAGES, PPN_BITS));
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val access_fault =
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2011-11-11 02:41:22 +01:00
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tlb_hit &&
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((status_s && !sx_array(tag_hit_addr).toBool) ||
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(status_u && !ux_array(tag_hit_addr).toBool));
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2011-11-13 08:39:43 +01:00
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2011-11-13 22:06:35 +01:00
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io.cpu.exception := access_fault; //|| outofrange;
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2011-11-12 09:25:06 +01:00
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io.cpu.req_rdy := Mux(status_vm, (state === s_ready) && (!r_cpu_req_val || tag_hit), Bool(true));
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io.cpu.resp_miss := tlb_miss || (state != s_ready);
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2011-11-12 03:48:34 +01:00
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io.cpu.resp_ppn := Mux(status_vm, tag_ram(tag_hit_addr), r_cpu_req_vpn(PPN_BITS-1,0)).toUFix;
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2011-11-09 23:52:17 +01:00
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io.ptw.req_val := (state === s_request);
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2011-11-10 06:54:11 +01:00
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io.ptw.req_vpn := r_refill_tag(VPN_BITS-1,0);
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2011-11-11 02:41:22 +01:00
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2011-11-09 23:52:17 +01:00
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// control state machine
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switch (state) {
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is (s_ready) {
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2011-11-11 02:41:22 +01:00
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when (tlb_miss) {
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2011-11-09 23:52:17 +01:00
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state <== s_request;
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}
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}
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is (s_request) {
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when (io.ptw.req_rdy) {
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state <== s_wait;
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}
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}
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is (s_wait) {
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2011-11-10 06:54:11 +01:00
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when (io.ptw.resp_val || io.ptw.resp_err) {
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2011-11-09 23:52:17 +01:00
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state <== s_ready;
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}
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}
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}
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}
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}
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