rocket-chip/vsim/Makefile

#=======================================================================
# Makefile for Verilog simulation w/ VCS
#-----------------------------------------------------------------------
# Yunsup Lee (yunsup@cs.berkeley.edu)
#
# This makefile will build a rtl simulator and run various tests to
# verify proper functionality.
#

default: all

base_dir = $(abspath ..)
generated_dir = $(abspath ./generated-src)
VLSI_MEM_GEN ?= $(base_dir)/scripts/vlsi_mem_gen
mem_gen = $(VLSI_MEM_GEN)
sim_dir = .
output_dir = $(sim_dir)/output

BACKEND ?= v
TB ?= TestDriver

include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag
ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
-include $(generated_dir)/$(long_name).d
endif
include $(base_dir)/vsim/Makefrag-verilog

all: $(simv)
debug: $(simv_debug)

clean:
	rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)

.PHONY: default all debug clean
update for rocket-chip release 2014-09-01 05:26:55 +02:00			`#=======================================================================`
			`# Makefile for Verilog simulation w/ VCS`
			`#-----------------------------------------------------------------------`
			`# Yunsup Lee (yunsup@cs.berkeley.edu)`
			`#`
			`# This makefile will build a rtl simulator and run various tests to`
			`# verify proper functionality.`
			`#`

			`default: all`

			`base_dir = $(abspath ..)`
			`generated_dir = $(abspath ./generated-src)`
tilelink: add mask rom 2017-08-01 06:12:45 +02:00			`VLSI_MEM_GEN ?= $(base_dir)/scripts/vlsi_mem_gen`
allow override of vlsi_mem_gen script 2016-08-24 02:05:09 +02:00			`mem_gen = $(VLSI_MEM_GEN)`
update for rocket-chip release 2014-09-01 05:26:55 +02:00			`sim_dir = .`
			`output_dir = $(sim_dir)/output`

Add CHISEL_VERSION make argument This allows users to specify if they want to build RocketChip against Chisel 2 or 3. Since Chisel 3 is now open source we can add these submodule pointers directly to avoid a fork of upstream. 2016-03-06 02:19:53 +01:00			`BACKEND ?= v`
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations. 2016-08-16 07:03:03 +02:00			`TB ?= TestDriver`
further generalize fpga/vlsi builds 2014-09-08 09:21:57 +02:00
add verilog target to build without simulator 2014-09-04 02:28:45 +02:00			`include $(base_dir)/Makefrag`
fix problem introduced with verilog generation in vsim/fsim 2014-09-04 18:49:57 +02:00			`include $(sim_dir)/Makefrag`
More accurate conditional include of generated .d make fragment (#222) 2016-08-25 23:42:04 +02:00			`ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)`
Use PROJECT rather than MODEL in name of binary and generated src files. 2016-09-19 22:23:17 +02:00			`-include $(generated_dir)/$(long_name).d`
Don't re-generate the .d files on "make clean" 2015-11-12 09:41:55 +01:00			`endif`
Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used 2015-07-28 09:23:31 +02:00			`include $(base_dir)/vsim/Makefrag-verilog`
update for rocket-chip release 2014-09-01 05:26:55 +02:00
			`all: $(simv)`
add CONFIG to the name of simulator executable 2014-09-12 07:11:58 +02:00			`debug: $(simv_debug)`
update for rocket-chip release 2014-09-01 05:26:55 +02:00
			`clean:`
fix problem introduced with verilog generation in vsim/fsim 2014-09-04 18:49:57 +02:00			`rm -rf $(junk) simv* csrc .key DVE .h .a *.daidir $(generated_dir)`
add CONFIG to the name of simulator executable 2014-09-12 07:11:58 +02:00
			`.PHONY: default all debug clean`