2015-10-27 05:37:35 +01:00
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package groundtest
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import Chisel._
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import uncore._
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import junctions._
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2015-10-30 20:49:57 +01:00
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import rocket._
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2015-10-27 05:37:35 +01:00
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import scala.util.Random
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import cde.{Parameters, Field}
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case object NGeneratorsPerTile extends Field[Int]
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case object NGeneratorTiles extends Field[Int]
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2015-11-01 01:43:25 +01:00
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case object GenerateUncached extends Field[Boolean]
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case object GenerateCached extends Field[Boolean]
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2015-10-27 05:37:35 +01:00
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trait HasGeneratorParams {
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implicit val p: Parameters
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val nGensPerTile = p(NGeneratorsPerTile)
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val nGenTiles = p(NGeneratorTiles)
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val nGens = nGensPerTile * nGenTiles
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2015-11-01 01:43:25 +01:00
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val genUncached = p(GenerateUncached)
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val genCached = p(GenerateCached)
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2015-10-27 05:37:35 +01:00
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}
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2015-10-27 07:09:36 +01:00
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class UncachedTileLinkGenerator(id: Int)
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2015-10-27 05:37:35 +01:00
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(implicit p: Parameters) extends TLModule()(p) with HasGeneratorParams {
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private val tlBlockOffset = tlBeatAddrBits + tlByteAddrBits
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2015-11-01 01:43:08 +01:00
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private val wordBits = 64
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private val wordOffset = log2Up(wordBits / 8)
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private val maxAddress = (p(MMIOBase) >> wordOffset).toInt / 2
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2015-10-27 05:37:35 +01:00
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private val totalRequests = maxAddress / nGens
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2015-10-27 07:09:36 +01:00
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val io = new Bundle {
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2015-10-28 00:42:31 +01:00
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val mem = new ClientUncachedTileLinkIO
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2015-10-27 07:09:36 +01:00
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val finished = Bool(OUTPUT)
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}
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2015-10-27 05:37:35 +01:00
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val (s_start :: s_put :: s_get :: s_finished :: Nil) = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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2015-11-01 01:43:08 +01:00
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val (req_cnt, req_wrap) = Counter(io.mem.grant.fire() && state === s_get, totalRequests)
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2015-10-27 05:37:35 +01:00
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val sending = Reg(init = Bool(false))
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when (state === s_start) {
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sending := Bool(true)
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state := s_put
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}
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when (state === s_put) {
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2015-11-01 01:43:08 +01:00
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when (io.mem.acquire.fire()) { sending := Bool(false) }
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2015-10-28 00:42:31 +01:00
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when (io.mem.grant.fire()) { sending := Bool(true); state := s_get }
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2015-10-27 05:37:35 +01:00
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}
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when (state === s_get) {
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2015-10-28 00:42:31 +01:00
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when (io.mem.acquire.fire()) { sending := Bool(false) }
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2015-11-01 01:43:08 +01:00
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when (io.mem.grant.fire()) {
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2015-10-27 05:37:35 +01:00
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sending := Bool(true)
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state := Mux(req_wrap, s_finished, s_put)
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}
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}
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io.finished := (state === s_finished)
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2015-11-01 01:43:08 +01:00
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val full_addr = Cat(req_cnt, UInt(id, log2Up(nGens)), UInt(0, wordOffset))
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val addr_block = full_addr >> UInt(tlBlockOffset)
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val addr_beat = full_addr(tlBlockOffset - 1, tlByteAddrBits)
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val addr_byte = full_addr(tlByteAddrBits - 1, 0)
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2015-10-27 05:55:04 +01:00
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val data_prefix = Cat(UInt(id, log2Up(nGens)), req_cnt)
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2015-11-01 01:43:08 +01:00
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val word_data = Wire(UInt(width = wordBits))
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word_data := Cat(data_prefix, full_addr)
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val beat_data = Fill(tlDataBits / wordBits, word_data)
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val wshift = Cat(full_addr(tlByteAddrBits - 1, wordOffset), UInt(0, wordOffset))
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val wmask = Fill(wordBits / 8, Bits(1, 1)) << wshift
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2015-10-27 05:37:35 +01:00
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2015-11-01 01:43:08 +01:00
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val put_acquire = Put(
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2015-10-27 05:37:35 +01:00
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client_xact_id = UInt(0),
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addr_block = addr_block,
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2015-11-01 01:43:08 +01:00
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addr_beat = addr_beat,
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data = beat_data,
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wmask = Some(wmask))
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2015-10-27 05:37:35 +01:00
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2015-11-01 01:43:08 +01:00
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val get_acquire = Get(
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2015-10-27 05:37:35 +01:00
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client_xact_id = UInt(0),
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2015-11-01 01:43:08 +01:00
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addr_block = addr_block,
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addr_beat = addr_beat,
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addr_byte = addr_byte,
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operand_size = MT_D,
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alloc = Bool(true))
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2015-10-27 05:37:35 +01:00
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2015-10-28 00:42:31 +01:00
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io.mem.acquire.valid := sending
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io.mem.acquire.bits := Mux(state === s_put, put_acquire, get_acquire)
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io.mem.grant.ready := !sending
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2015-10-27 05:37:35 +01:00
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2015-11-01 01:43:08 +01:00
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assert(!io.mem.grant.valid || state =/= s_get ||
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io.mem.grant.bits.data(63, 0) === word_data,
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2015-10-30 20:49:57 +01:00
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s"Get received incorrect data in uncached generator ${id}")
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2015-10-27 05:37:35 +01:00
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}
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2015-10-28 00:42:31 +01:00
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2015-10-30 20:49:57 +01:00
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class HellaCacheGenerator(id: Int)
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(implicit p: Parameters) extends L1HellaCacheModule()(p) with HasGeneratorParams {
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private val wordOffset = log2Up(coreDataBits / 8)
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private val maxAddress = (p(MMIOBase) >> wordOffset).toInt
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private val startAddress = maxAddress / 2
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private val totalRequests = (maxAddress - startAddress) / nGens
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val io = new Bundle {
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val finished = Bool(OUTPUT)
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val mem = new HellaCacheIO
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}
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val (s_start :: s_write :: s_read :: s_finished :: Nil) = Enum(Bits(), 4)
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val state = Reg(init = s_start)
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val sending = Reg(init = Bool(false))
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val (req_cnt, req_wrap) = Counter(
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io.mem.resp.valid && io.mem.resp.bits.has_data, totalRequests)
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val req_addr = UInt(startAddress) +
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Cat(req_cnt, UInt(id, log2Up(nGens)), UInt(0, wordOffset))
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val req_data = Cat(UInt(id, log2Up(nGens)), req_cnt, req_addr)
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io.mem.req.valid := sending
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io.mem.req.bits.addr := req_addr
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io.mem.req.bits.data := req_data
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io.mem.req.bits.typ := MT_D
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io.mem.req.bits.cmd := Mux(state === s_write, M_XWR, M_XRD)
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io.mem.req.bits.tag := UInt(0)
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io.mem.req.bits.kill := Bool(false)
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io.mem.req.bits.phys := Bool(true)
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when (state === s_start) { sending := Bool(true); state := s_write }
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when (io.mem.req.fire()) { sending := Bool(false) }
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when (io.mem.resp.valid) {
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sending := Bool(true)
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state := Mux(state === s_write, s_read, s_write)
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}
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when (req_wrap) { sending := Bool(false); state := s_finished }
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assert(!io.mem.resp.valid || !io.mem.resp.bits.has_data ||
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io.mem.resp.bits.data === req_data,
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s"Received incorrect data in cached generator ${id}")
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}
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