2013-01-25 08:56:45 +01:00
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#include "htif_emulator.h"
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2012-10-02 04:30:11 +02:00
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#include "emulator.h"
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2012-12-04 16:04:26 +01:00
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#include "mm.h"
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#include "mm_dramsim2.h"
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2013-01-25 08:56:45 +01:00
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#include <fcntl.h>
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#include <signal.h>
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#include <stdio.h>
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#include <stdlib.h>
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2013-03-26 01:01:13 +01:00
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#include <unistd.h>
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2012-10-02 04:30:11 +02:00
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2013-01-25 08:56:45 +01:00
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htif_emulator_t* htif;
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void handle_sigterm(int sig)
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2012-11-20 14:40:44 +01:00
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{
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2013-01-25 08:56:45 +01:00
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htif->stop();
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2012-11-20 14:40:44 +01:00
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}
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2012-10-02 04:30:11 +02:00
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int main(int argc, char** argv)
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{
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unsigned random_seed = (unsigned)time(NULL) ^ (unsigned)getpid();
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2013-10-29 21:24:09 +01:00
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uint64_t max_cycles = -1;
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2012-10-02 04:30:11 +02:00
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uint64_t trace_count = 0;
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2013-10-29 21:24:09 +01:00
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int ret = 0;
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2012-10-02 04:30:11 +02:00
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const char* vcd = NULL;
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const char* loadmem = NULL;
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2013-06-13 19:53:23 +02:00
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FILE *vcdfile = NULL;
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2012-12-04 16:04:26 +01:00
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bool dramsim2 = false;
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2013-06-13 19:53:23 +02:00
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bool log = false;
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2012-11-20 14:40:44 +01:00
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2012-10-02 04:30:11 +02:00
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for (int i = 1; i < argc; i++)
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{
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std::string arg = argv[i];
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2013-01-25 08:56:45 +01:00
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if (arg.substr(0, 2) == "-v")
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2012-10-02 04:30:11 +02:00
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vcd = argv[i]+2;
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else if (arg.substr(0, 2) == "-s")
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random_seed = atoi(argv[i]+2);
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2013-01-25 08:56:45 +01:00
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else if (arg == "+dramsim")
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dramsim2 = true;
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else if (arg == "+verbose")
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log = true;
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else if (arg.substr(0, 12) == "+max-cycles=")
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max_cycles = atoll(argv[i]+12);
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2012-10-02 04:30:11 +02:00
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else if (arg.substr(0, 9) == "+loadmem=")
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loadmem = argv[i]+9;
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2013-01-25 08:56:45 +01:00
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}
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2012-10-02 04:30:11 +02:00
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2012-11-18 02:25:43 +01:00
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const int disasm_len = 24;
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2012-10-02 04:30:11 +02:00
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if (vcd)
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{
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// Create a VCD file
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vcdfile = strcmp(vcd, "-") == 0 ? stdout : fopen(vcd, "w");
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assert(vcdfile);
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fprintf(vcdfile, "$scope module Testbench $end\n");
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2012-11-17 16:21:29 +01:00
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fprintf(vcdfile, "$var reg %d NDISASM_WB wb_instruction $end\n", disasm_len*8);
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fprintf(vcdfile, "$var reg 64 NCYCLE cycle $end\n");
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2012-10-02 04:30:11 +02:00
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fprintf(vcdfile, "$upscope $end\n");
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}
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// The chisel generated code
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Top_t tile;
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srand(random_seed);
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tile.init(random_seed != 0);
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2013-05-02 13:58:43 +02:00
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// Instantiate and initialize main memory
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mm_t* mm = dramsim2 ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
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mm->init(MEM_SIZE, tile.Top__io_mem_resp_bits_data.width()/8, LINE_SIZE);
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if (loadmem)
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load_mem(mm->get_data(), loadmem);
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2013-01-25 08:56:45 +01:00
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// Instantiate HTIF
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2013-01-27 01:13:14 +01:00
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htif = new htif_emulator_t(std::vector<std::string>(argv + 1, argv + argc));
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2013-01-25 08:56:45 +01:00
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int htif_bits = tile.Top__io_host_in_bits.width();
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assert(htif_bits % 8 == 0 && htif_bits <= val_n_bits());
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signal(SIGTERM, handle_sigterm);
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2012-10-02 04:30:11 +02:00
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// reset for a few cycles to support pipelined reset
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tile.Top__io_host_in_valid = LIT<1>(0);
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tile.Top__io_host_out_ready = LIT<1>(0);
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2012-10-19 02:51:41 +02:00
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tile.Top__io_mem_backup_en = LIT<1>(0);
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2012-10-02 04:30:11 +02:00
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for (int i = 0; i < 10; i++)
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{
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tile.clock_lo(LIT<1>(1));
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tile.clock_hi(LIT<1>(1));
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}
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2013-10-29 21:24:09 +01:00
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while (!htif->done() && trace_count < max_cycles)
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2012-10-02 04:30:11 +02:00
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{
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2012-12-04 16:04:26 +01:00
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tile.Top__io_mem_req_cmd_ready = LIT<1>(mm->req_cmd_ready());
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tile.Top__io_mem_req_data_ready = LIT<1>(mm->req_data_ready());
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tile.Top__io_mem_resp_valid = LIT<1>(mm->resp_valid());
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tile.Top__io_mem_resp_bits_tag = LIT<64>(mm->resp_tag());
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2014-01-16 21:44:29 +01:00
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memcpy(tile.Top__io_mem_resp_bits_data.values, mm->resp_data(), tile.Top__io_mem_resp_bits_data.width()/8);
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2012-12-04 16:04:26 +01:00
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tile.clock_lo(LIT<1>(0));
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mm->tick(
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2012-10-02 04:30:11 +02:00
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tile.Top__io_mem_req_cmd_valid.lo_word(),
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tile.Top__io_mem_req_cmd_bits_rw.lo_word(),
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tile.Top__io_mem_req_cmd_bits_addr.lo_word(),
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tile.Top__io_mem_req_cmd_bits_tag.lo_word(),
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tile.Top__io_mem_req_data_valid.lo_word(),
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2014-01-16 21:44:29 +01:00
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tile.Top__io_mem_req_data_bits_data.values,
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2013-05-02 13:58:43 +02:00
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tile.Top__io_mem_resp_ready.to_bool()
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2012-10-02 04:30:11 +02:00
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);
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2012-10-19 02:51:41 +02:00
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if (tile.Top__io_host_clk_edge.to_bool())
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{
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2013-02-21 01:11:21 +01:00
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static bool htif_in_valid = false;
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static val_t htif_in_bits;
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if (tile.Top__io_host_in_ready.to_bool() || !htif_in_valid)
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htif_in_valid = htif->recv_nonblocking(&htif_in_bits, htif_bits/8);
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tile.Top__io_host_in_valid = LIT<1>(htif_in_valid);
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tile.Top__io_host_in_bits = LIT<64>(htif_in_bits);
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2013-01-25 08:56:45 +01:00
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if (tile.Top__io_host_out_valid.to_bool())
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2014-01-16 21:44:29 +01:00
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htif->send(tile.Top__io_host_out_bits.values, htif_bits/8);
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2013-02-21 01:11:21 +01:00
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tile.Top__io_host_out_ready = LIT<1>(1);
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2012-10-19 02:51:41 +02:00
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}
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2012-10-02 04:30:11 +02:00
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2013-06-13 19:53:23 +02:00
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if (log)
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2014-03-05 01:38:34 +01:00
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tile.print(stderr);
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2013-06-13 19:53:23 +02:00
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if (vcd)
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tile.dump(vcdfile, trace_count);
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2012-10-02 04:30:11 +02:00
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tile.clock_hi(LIT<1>(0));
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trace_count++;
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}
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if (vcd)
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fclose(vcdfile);
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2013-10-29 21:24:09 +01:00
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if (htif->exit_code())
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2012-10-02 04:30:11 +02:00
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{
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2014-03-17 23:35:17 +01:00
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fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %lld cycles\n", htif->exit_code(), random_seed, (long long)trace_count);
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2013-10-29 21:24:09 +01:00
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ret = htif->exit_code();
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2012-10-02 04:30:11 +02:00
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}
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2013-10-29 21:24:09 +01:00
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else if (trace_count == max_cycles)
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{
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fprintf(stderr, "*** FAILED *** (timeout) after %lld cycles\n", (long long)trace_count);
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ret = 2;
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}
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delete htif;
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2012-10-02 04:30:11 +02:00
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2013-10-29 21:24:09 +01:00
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return ret;
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2012-10-02 04:30:11 +02:00
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}
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