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rocket-chip/emulator/Makefile

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Makefile
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Add missing changes to emulator/Makefile
2015-07-30 02:57:02 +02:00
default: all
update for rocket-chip release
2014-09-01 05:26:55 +02:00
base_dir = $(abspath ..)
Add missing changes to emulator/Makefile
2015-07-30 02:57:02 +02:00
generated_dir = $(abspath ./generated-src)
Added generated-src-debug to make clean target
2015-09-12 04:07:33 +02:00
generated_dir_debug = $(abspath ./generated-src-debug)
commit awesome vlsi/energy scripts
2013-05-01 11:58:53 +02:00
sim_dir = .
update for rocket-chip release
2014-09-01 05:26:55 +02:00
output_dir = $(sim_dir)/output
Update Makefile Change default shell to bash shell.
2015-04-07 00:05:43 +02:00
commit awesome vlsi/energy scripts
2013-05-01 11:58:53 +02:00
include $(base_dir)/Makefrag
everything to get emulator working
2012-10-02 04:30:11 +02:00
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
CXXSRCS := emulator SimDTM
CXXFLAGS := $(CXXFLAGS) -std=c++11 -I$(RISCV)/include -I$(base_dir)/csrc
LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(abspath $(sim_dir)) -lfesvr -lpthread
Speed up C++ compilation
2014-01-31 21:25:19 +01:00
Add missing changes to emulator/Makefile
2015-07-30 02:57:02 +02:00
emu = emulator-$(MODEL)-$(CONFIG)
emu_debug = emulator-$(MODEL)-$(CONFIG)-debug
replace emulator with verilator for chisel3
2016-06-08 10:39:40 +02:00
include $(sim_dir)/Makefrag-verilator
Reintroduced multiple emulator backend directories Fixes a "make -j" concurrency bug due to deleting files that another parallel rule depends on.
2015-09-11 02:14:23 +02:00
Add missing changes to emulator/Makefile
2015-07-30 02:57:02 +02:00
all: $(emu)
debug: $(emu_debug)
everything to get emulator working
2012-10-02 04:30:11 +02:00
clean:
Added generated-src-debug to make clean target
2015-09-12 04:07:33 +02:00
rm -rf *.o *.a emulator-* $(generated_dir) $(generated_dir_debug) DVEfiles $(output_dir)
first crack at continuous compilation/testing flow try it out: cd emulator; make test
2012-10-19 13:09:07 +02:00
test:
Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes
2013-08-20 04:54:41 +02:00
cd $(base_dir) && $(SBT) "~make $(CURDIR) run-fast $(CHISEL_ARGS)"
everything to get emulator working
2012-10-02 04:30:11 +02:00
Add missing changes to emulator/Makefile
2015-07-30 02:57:02 +02:00
.PHONY: default all debug clean test
everything to get emulator working
2012-10-02 04:30:11 +02:00
#--------------------------------------------------------------------
# Run assembly tests and benchmarks
#--------------------------------------------------------------------
More accurate conditional include of generated .d make fragment (#222)
2016-08-25 23:42:04 +02:00
ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
Use PROJECT rather than MODEL in name of binary and generated src files.
2016-09-19 22:23:17 +02:00
-include $(generated_dir)/$(long_name).d
Don't re-generate the .d files on "make clean"
2015-11-12 09:41:55 +01:00
endif
Added generated-src-debug to make clean target
2015-09-12 04:07:33 +02:00
replace emulator with verilator for chisel3
2016-06-08 10:39:40 +02:00
$(output_dir)/%.run: $(output_dir)/% $(emu)
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
./$(emu) +max-cycles=$(timeout_cycles) $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
everything to get emulator working
2012-10-02 04:30:11 +02:00
replace emulator with verilator for chisel3
2016-06-08 10:39:40 +02:00
$(output_dir)/%.out: $(output_dir)/% $(emu)
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
./$(emu) +max-cycles=$(timeout_cycles) +verbose $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
everything to get emulator working
2012-10-02 04:30:11 +02:00
replace emulator with verilator for chisel3
2016-06-08 10:39:40 +02:00
$(output_dir)/%.vcd: $(output_dir)/% $(emu_debug)
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
./$(emu_debug) +max-cycles=$(timeout_cycles) +verbose -v$@ $< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
everything to get emulator working
2012-10-02 04:30:11 +02:00
replace emulator with verilator for chisel3
2016-06-08 10:39:40 +02:00
$(output_dir)/%.vpd: $(output_dir)/% $(emu_debug)
use a named pipe for VCD -> VPD conversion
2013-03-26 00:19:19 +01:00
rm -rf $@.vcd && mkfifo $@.vcd
don't pipe stdout to vcd2vpd
2013-03-26 01:01:13 +01:00
vcd2vpd $@.vcd $@ > /dev/null &
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
./$(emu_debug) +max-cycles=$(timeout_cycles) +verbose -v$@.vcd $< $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
everything to get emulator working
2012-10-02 04:30:11 +02:00
first cut at parameter-based testing
2015-07-13 23:54:26 +02:00
run: run-asm-tests run-bmark-tests
run-debug: run-asm-tests-debug run-bmark-tests-debug
run-fast: run-asm-tests-fast run-bmark-tests-fast
.PHONY: run-asm-tests run-bmarks-test
.PHONY: run-asm-tests-debug run-bmark-tests-debug
tease out reference-chip specific stuff
2014-09-10 05:49:28 +02:00
.PHONY: run run-debug run-fast
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