2012-02-26 02:09:26 +01:00
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package rocket
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2011-10-26 08:02:47 +02:00
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2012-10-08 07:37:29 +02:00
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import Chisel._
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2012-11-18 02:24:08 +01:00
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import Util._
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2013-11-08 00:42:03 +01:00
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import uncore.HTIFIO
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2011-10-26 08:02:47 +02:00
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2014-08-02 03:01:08 +02:00
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case object FPUParams extends Field[PF]
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2014-08-08 21:23:02 +02:00
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case object BuildFPU extends Field[Option[() => FPU]]
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2014-08-02 03:01:08 +02:00
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2014-08-08 21:23:02 +02:00
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class RocketIO extends Bundle
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2011-10-26 08:02:47 +02:00
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{
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2014-08-08 21:23:02 +02:00
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val host = new HTIFIO
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val imem = new CPUFrontendIO
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val dmem = new HellaCacheIO
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val ptw = new DatapathPTWIO().flip
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2013-09-15 00:31:50 +02:00
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val rocc = new RoCCInterface().flip
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2011-10-26 08:02:47 +02:00
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}
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2014-08-08 21:23:02 +02:00
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class Core extends Module
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2011-10-26 08:02:47 +02:00
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{
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2014-08-08 21:23:02 +02:00
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val io = new RocketIO
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2011-11-09 23:52:17 +01:00
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2014-08-08 21:23:02 +02:00
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val ctrl = Module(new Control)
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2013-08-12 19:39:11 +02:00
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val dpath = Module(new Datapath)
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2011-10-26 08:02:47 +02:00
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2014-08-08 21:23:02 +02:00
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if (!params(BuildFPU).isEmpty) {
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val fpu = Module(params(BuildFPU).get(),params(FPUParams))
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2013-09-15 00:31:50 +02:00
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dpath.io.fpu <> fpu.io.dpath
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ctrl.io.fpu <> fpu.io.ctrl
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2014-03-05 01:32:09 +01:00
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}
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2013-09-15 00:31:50 +02:00
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2012-11-06 17:13:44 +01:00
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ctrl.io.dpath <> dpath.io.ctrl
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dpath.io.host <> io.host
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ctrl.io.imem <> io.imem
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dpath.io.imem <> io.imem
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2013-09-13 07:34:38 +02:00
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ctrl.io.dmem <> io.dmem
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dpath.io.dmem <> io.dmem
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2011-11-09 23:52:17 +01:00
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2013-09-13 07:34:38 +02:00
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dpath.io.ptw <> io.ptw
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2012-11-06 17:13:44 +01:00
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2013-09-15 00:31:50 +02:00
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ctrl.io.rocc <> io.rocc
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dpath.io.rocc <> io.rocc
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2011-10-26 08:02:47 +02:00
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}
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