2016-11-28 01:16:37 +01:00
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// See LICENSE.Berkeley for license details.
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2014-09-13 00:31:38 +02:00
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2012-09-27 21:59:45 +02:00
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package uncore
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2012-10-16 03:52:48 +02:00
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package constants
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2012-09-27 21:59:45 +02:00
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import Chisel._
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2017-04-13 06:49:37 +02:00
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import _root_.util._
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2012-10-16 03:52:48 +02:00
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2013-07-25 08:22:36 +02:00
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object MemoryOpConstants extends MemoryOpConstants
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2012-10-16 03:52:48 +02:00
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trait MemoryOpConstants {
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2014-11-12 02:36:55 +01:00
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val NUM_XA_OPS = 9
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2013-04-04 07:13:51 +02:00
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val M_SZ = 5
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2017-01-31 22:54:02 +01:00
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def M_X = BitPat("b?????");
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def M_XRD = UInt("b00000"); // int load
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def M_XWR = UInt("b00001"); // int store
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def M_PFR = UInt("b00010"); // prefetch with intent to read
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def M_PFW = UInt("b00011"); // prefetch with intent to write
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def M_XA_SWAP = UInt("b00100");
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def M_FLUSH_ALL = UInt("b00101") // flush all lines
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def M_XLR = UInt("b00110");
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def M_XSC = UInt("b00111");
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def M_XA_ADD = UInt("b01000");
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def M_XA_XOR = UInt("b01001");
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def M_XA_OR = UInt("b01010");
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def M_XA_AND = UInt("b01011");
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def M_XA_MIN = UInt("b01100");
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def M_XA_MAX = UInt("b01101");
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def M_XA_MINU = UInt("b01110");
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def M_XA_MAXU = UInt("b01111");
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def M_FLUSH = UInt("b10000") // write back dirty data and cede R/W permissions
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2017-05-02 12:04:41 +02:00
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def M_PWR = UInt("b10001") // partial (masked) store
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def M_PRODUCE = UInt("b10010") // write back dirty data and cede W permissions
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2017-01-31 22:54:02 +01:00
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def M_CLEAN = UInt("b10011") // write back dirty data and retain R/W permissions
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2017-03-14 21:54:49 +01:00
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def M_SFENCE = UInt("b10100") // flush TLB
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2012-11-16 11:37:56 +01:00
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2017-04-13 06:49:37 +02:00
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def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND)
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def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU)
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def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd)
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2015-07-28 11:46:23 +02:00
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def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
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2015-09-26 00:27:20 +02:00
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def isRead(cmd: UInt) = cmd === M_XRD || cmd === M_XLR || cmd === M_XSC || isAMO(cmd)
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2017-05-02 12:04:41 +02:00
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def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd)
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2015-07-28 11:46:23 +02:00
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def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
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2012-10-16 03:52:48 +02:00
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}
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2016-06-28 20:21:38 +02:00
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