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riscv/rocket-chip
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05e7501e7a60211f82d58db3eb3cf001537831a5
rocket-chip/src/main/scala
T
History
Wesley W. TerpstraandGitHub 05e7501e7a build: include chiselName and give an example of using it (#738)
2017-05-12 06:25:58 -07:00
..
config
Configs: use a uniform syntax without Match exceptions (#507)
2017-01-13 14:41:19 -08:00
coreplex
axi4: ToTL supporting pipelined MMIO
2017-05-01 22:53:40 -07:00
diplomacy
diplomacy: add legalize method to AddressSet
2017-05-10 12:54:24 -07:00
groundtest
Fix regression in groundtest DummyPTW
2017-03-28 00:56:14 -07:00
jtag
jtag: make it easier to assign MFR ID externally
2017-04-14 01:03:11 -07:00
junctions
debug: Remove older version of JTAG interface as it is superseded by the one in jtag package.
2017-03-27 21:25:37 -07:00
regmapper
regmapper: remove the Pipe in the RegMapper Queue
2017-04-19 21:37:37 -07:00
rocket
DTS tweaks (#740)
2017-05-12 05:32:57 -07:00
rocketchip
rocketchip: move the Error device to 0x3000
2017-05-01 22:53:41 -07:00
tile
local_interrupts: Correct off-by-1 if there is no SEIP
2017-05-02 21:55:25 -07:00
uncore
build: include chiselName and give an example of using it (#738)
2017-05-12 06:25:58 -07:00
unittest
unittest: put AtomicAutomata under regression
2017-04-14 15:13:39 -07:00
util
Support indexing 1-entry Seqs
2017-04-26 19:35:35 -07:00
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