1
0
rocket-chip/uncore/src/consts.scala

90 lines
2.4 KiB
Scala
Raw Normal View History

package uncore
2012-10-16 03:52:48 +02:00
package constants
import Chisel._
import scala.math.max
2012-10-16 03:52:48 +02:00
abstract trait CoherenceConfigConstants {
val ENABLE_SHARING: Boolean
val ENABLE_CLEAN_EXCLUSIVE: Boolean
}
trait UncoreConstants {
val NGLOBAL_XACTS = 8
val MASTER_XACT_ID_MAX_BITS = log2Up(NGLOBAL_XACTS)
2012-10-16 03:52:48 +02:00
val CACHE_DATA_SIZE_IN_BYTES = 1 << 6
}
trait CacheConstants extends UncoreConstants {
val OFFSET_BITS = log2Up(CACHE_DATA_SIZE_IN_BYTES)
}
2012-10-16 03:52:48 +02:00
trait TileLinkTypeConstants {
2013-01-22 02:17:26 +01:00
val ACQUIRE_TYPE_MAX_BITS = 2
val GRANT_TYPE_MAX_BITS = 3
val PROBE_TYPE_MAX_BITS = 2
val RELEASE_TYPE_MAX_BITS = 3
2012-10-16 03:52:48 +02:00
}
trait TileLinkSizeConstants extends
TileLinkTypeConstants
{
val CLIENT_XACT_ID_MAX_BITS = 10
2013-01-22 02:17:26 +01:00
val ACQUIRE_WRITE_MASK_BITS = 6
val ACQUIRE_SUBWORD_ADDR_BITS = 3
val ACQUIRE_ATOMIC_OP_BITS = 4
2012-10-16 03:52:48 +02:00
}
2012-10-16 03:52:48 +02:00
trait MemoryOpConstants {
val MT_X = Bits("b???", 3);
val MT_B = Bits("b000", 3);
val MT_H = Bits("b001", 3);
val MT_W = Bits("b010", 3);
val MT_D = Bits("b011", 3);
val MT_BU = Bits("b100", 3);
val MT_HU = Bits("b101", 3);
val MT_WU = Bits("b110", 3);
val M_X = Bits("b????", 4);
val M_XRD = Bits("b0000", 4); // int load
val M_XWR = Bits("b0001", 4); // int store
val M_PFR = Bits("b0010", 4); // prefetch with intent to read
val M_PFW = Bits("b0011", 4); // prefetch with intent to write
val M_FENCE = Bits("b0101", 4); // memory fence
val M_INV = Bits("b0110", 4); // write back and invalidate line
val M_CLN = Bits("b0111", 4); // write back line
val M_XA_ADD = Bits("b1000", 4);
val M_XA_SWAP = Bits("b1001", 4);
val M_XA_AND = Bits("b1010", 4);
val M_XA_OR = Bits("b1011", 4);
val M_XA_MIN = Bits("b1100", 4);
val M_XA_MAX = Bits("b1101", 4);
val M_XA_MINU = Bits("b1110", 4);
val M_XA_MAXU = Bits("b1111", 4);
def isAMO(cmd: Bits) = cmd(3)
2012-11-18 12:13:17 +01:00
def isPrefetch(cmd: Bits) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: Bits) = cmd === M_XRD || isAMO(cmd)
def isWrite(cmd: Bits) = cmd === M_XWR || isAMO(cmd)
2012-10-16 03:52:48 +02:00
}
2012-10-16 03:52:48 +02:00
trait MemoryInterfaceConstants extends
UncoreConstants with
TileLinkSizeConstants
{
val MEM_TAG_BITS = max(CLIENT_XACT_ID_MAX_BITS, MASTER_XACT_ID_MAX_BITS)
val MEM_DATA_BITS = 128
2012-10-16 03:52:48 +02:00
val REFILL_CYCLES = CACHE_DATA_SIZE_IN_BYTES*8/MEM_DATA_BITS
}
trait AddressConstants {
2012-11-27 05:54:56 +01:00
val PADDR_BITS = 32
val VADDR_BITS = 43;
val PGIDX_BITS = 13;
val PPN_BITS = PADDR_BITS-PGIDX_BITS;
val VPN_BITS = VADDR_BITS-PGIDX_BITS;
val ASID_BITS = 7;
val PERM_BITS = 6;
}