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rocket-chip/vsim/Makefrag-verilog

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Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used
2015-07-28 09:23:31 +02:00
#--------------------------------------------------------------------
# Verilog Generation
#--------------------------------------------------------------------
[testharness] vsim makefrag cleanup
2016-09-19 22:46:45 +02:00
firrtl = $(generated_dir)/$(long_name).fir
verilog = $(generated_dir)/$(long_name).v
Add CHISEL_VERSION make argument This allows users to specify if they want to build RocketChip against Chisel 2 or 3. Since Chisel 3 is now open source we can add these submodule pointers directly to avoid a fork of upstream.
2016-03-06 02:19:53 +01:00
# If I don't mark these as .SECONDARY then make will delete these internal
# files.
[testharness] vsim makefrag cleanup
2016-09-19 22:46:45 +02:00
.SECONDARY: $(firrtl) $(verilog)
Add firrtl and verilog Makefile targets to vsim
2016-09-15 02:33:39 +02:00
Artefact output (#545) * build: stop using empty .prm file * generator: general-purpose mechanism for creating elaboration artefacts
2017-02-03 04:24:55 +01:00
$(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
Add CHISEL_VERSION make argument This allows users to specify if they want to build RocketChip against Chisel 2 or 3. Since Chisel 3 is now open source we can add these submodule pointers directly to avoid a fork of upstream.
2016-03-06 02:19:53 +01:00
mkdir -p $(dir $@)
Bump chisel3 and firrtl and bump sbt to version 1.0.4 sbt bump must be accompanied by bump to chisel3 and firrtl using sbt 1.0.4
2017-12-13 03:46:51 +01:00
cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
Add CHISEL_VERSION make argument This allows users to specify if they want to build RocketChip against Chisel 2 or 3. Since Chisel 3 is now open source we can add these submodule pointers directly to avoid a fork of upstream.
2016-03-06 02:19:53 +01:00
Use % in makefrag-verilog to prevent double firrtl execution (#452) * Use % in makefrag-verilog to prevent double firrtl execution
2016-11-25 10:50:01 +01:00
$(generated_dir)/%.v $(generated_dir)/%.conf: $(generated_dir)/%.fir $(FIRRTL_JAR)
Add CHISEL_VERSION make argument This allows users to specify if they want to build RocketChip against Chisel 2 or 3. Since Chisel 3 is now open source we can add these submodule pointers directly to avoid a fork of upstream.
2016-03-06 02:19:53 +01:00
mkdir -p $(dir $@)
Bump Chisel and FIRRTL for annotations refactor (#1261) Also brings in an autoclonetype enhancement and some bug fixes
2018-03-07 19:22:38 +01:00
$(FIRRTL) -i $< -o $(generated_dir)/$*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$*.conf -faf $(generated_dir)/$*.anno.json
Bump FIRRTL to instantiate Sequential Memory Macros
2016-09-06 23:48:28 +02:00
Use PROJECT rather than MODEL in name of binary and generated src files.
2016-09-19 22:23:17 +02:00
$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen)
Bump FIRRTL to instantiate Sequential Memory Macros
2016-09-06 23:48:28 +02:00
cd $(generated_dir) && \
mem_gen failure doesn't create the target
2016-08-24 21:52:24 +02:00
rm -f $@ && \
Use PROJECT rather than MODEL in name of binary and generated src files.
2016-09-19 22:23:17 +02:00
$(mem_gen) $(generated_dir)/$(long_name).conf >> $@.tmp && \
mem_gen failure doesn't create the target
2016-08-24 21:52:24 +02:00
mv $@.tmp $@
Add CHISEL_VERSION make argument This allows users to specify if they want to build RocketChip against Chisel 2 or 3. Since Chisel 3 is now open source we can add these submodule pointers directly to avoid a fork of upstream.
2016-03-06 02:19:53 +01:00
update for rocket-chip release
2014-09-01 05:26:55 +02:00
#--------------------------------------------------------------------
# Run
#--------------------------------------------------------------------
Do allow make to remove .vpd files on Ctrl-C
2017-03-30 08:46:18 +02:00
.PRECIOUS: $(output_dir)/%.vpd
update for rocket-chip release
2014-09-01 05:26:55 +02:00
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(output_dir)/%.run: $(output_dir)/% $(simv)
Fix VCS argument parsing (#1266) * Add +permissive/+permissive-off for VCS args This adds guards around Verilog/VCS options for VCS calls with HTIF's new `+permissive`/`+permissive-off` options. This enables HTIF to permissively parse all options inside one of these guards while not erroring on unknonw commands. This is necessary for VCS, unlike with the emulator, as HTIF is giving all commands as opposed to only host and target arguments (like with Verilator/emulator.cc). * Bump riscv-tools for fesvr VCS fix * Bump riscv-rools/riscv-fesvr (VCS stderr fix) Fixes #1266 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-08 07:59:04 +01:00
cd $(sim_dir) && $(exec_simv) +permissive +max-cycles=$(timeout_cycles) +permissive-off $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
first cut at parameter-based testing
2015-07-13 23:54:26 +02:00
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(output_dir)/%.out: $(output_dir)/% $(simv)
Fix VCS argument parsing (#1266) * Add +permissive/+permissive-off for VCS args This adds guards around Verilog/VCS options for VCS calls with HTIF's new `+permissive`/`+permissive-off` options. This enables HTIF to permissively parse all options inside one of these guards while not erroring on unknonw commands. This is necessary for VCS, unlike with the emulator, as HTIF is giving all commands as opposed to only host and target arguments (like with Verilator/emulator.cc). * Bump riscv-tools for fesvr VCS fix * Bump riscv-rools/riscv-fesvr (VCS stderr fix) Fixes #1266 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-08 07:59:04 +01:00
cd $(sim_dir) && $(exec_simv) +permissive +verbose +max-cycles=$(timeout_cycles) +permissive-off $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
update for rocket-chip release
2014-09-01 05:26:55 +02:00
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(output_dir)/%.vcd: $(output_dir)/% $(simv_debug)
Fix VCS argument parsing (#1266) * Add +permissive/+permissive-off for VCS args This adds guards around Verilog/VCS options for VCS calls with HTIF's new `+permissive`/`+permissive-off` options. This enables HTIF to permissively parse all options inside one of these guards while not erroring on unknonw commands. This is necessary for VCS, unlike with the emulator, as HTIF is giving all commands as opposed to only host and target arguments (like with Verilator/emulator.cc). * Bump riscv-tools for fesvr VCS fix * Bump riscv-rools/riscv-fesvr (VCS stderr fix) Fixes #1266 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-08 07:59:04 +01:00
cd $(sim_dir) && $(exec_simv_debug) +permissive +verbose +vcdfile=$@ +max-cycles=$(timeout_cycles) +permissive-off $< $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
update for rocket-chip release
2014-09-01 05:26:55 +02:00
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(output_dir)/%.vpd: $(output_dir)/% $(simv_debug)
Fix VCS argument parsing (#1266) * Add +permissive/+permissive-off for VCS args This adds guards around Verilog/VCS options for VCS calls with HTIF's new `+permissive`/`+permissive-off` options. This enables HTIF to permissively parse all options inside one of these guards while not erroring on unknonw commands. This is necessary for VCS, unlike with the emulator, as HTIF is giving all commands as opposed to only host and target arguments (like with Verilator/emulator.cc). * Bump riscv-tools for fesvr VCS fix * Bump riscv-rools/riscv-fesvr (VCS stderr fix) Fixes #1266 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-08 07:59:04 +01:00
cd $(sim_dir) && $(exec_simv_debug) +permissive +verbose +vcdplusfile=$@ +max-cycles=$(timeout_cycles) +permissive-off $< $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
update for rocket-chip release
2014-09-01 05:26:55 +02:00
Write test harness in Chisel This is an unavoidably invasive commit, because it affects the unit tests (which formerly exited using stop()), the test harness Verilog generator (since it is no longer necessary), and the DRAM model (since it is no longer connected). However, this should substantially reduce the effort of building test harnesses in the future, since manual or semi-automatic Verilog writing should no longer be necessary. Furthermore, there is now very little duplication of effort between the Verilator and VCS test harnesses. This commit removes support for DRAMsim, which is a bit of an unfortunate consequence. The main blocker is the lack of Verilog parameterization for BlackBox. It would be straightforward to revive DRAMsim once support for that feature is added to Chisel and FIRRTL. But that might not even be necessary, as we move towards synthesizable DRAM models and FAME-1 transformations.
2016-08-16 07:03:03 +02:00
$(output_dir)/%.saif: $(output_dir)/% $(simv_debug)
Fix VCS argument parsing (#1266) * Add +permissive/+permissive-off for VCS args This adds guards around Verilog/VCS options for VCS calls with HTIF's new `+permissive`/`+permissive-off` options. This enables HTIF to permissively parse all options inside one of these guards while not erroring on unknonw commands. This is necessary for VCS, unlike with the emulator, as HTIF is giving all commands as opposed to only host and target arguments (like with Verilator/emulator.cc). * Bump riscv-tools for fesvr VCS fix * Bump riscv-rools/riscv-fesvr (VCS stderr fix) Fixes #1266 Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-08 07:59:04 +01:00
cd $(sim_dir) && rm -f $(output_dir)/pipe-$*.vcd && vcd2saif -input $(output_dir)/pipe-$*.vcd -pipe "$(exec_simv_debug) +permissive +verbose +vcdfile=$(output_dir)/pipe-$*.vcd +max-cycles=$(bmark_timeout_cycles) +permissive-off $<" -output $@ > $(patsubst %.saif,%.out,$@) 2>&1
update for rocket-chip release
2014-09-01 05:26:55 +02:00
Fixed run-bmark-tests make target in vsim
2015-09-10 07:37:47 +02:00
run: run-asm-tests run-bmark-tests
run-debug: run-asm-tests-debug run-bmark-tests-debug
first cut at parameter-based testing
2015-07-13 23:54:26 +02:00
run-fast: run-asm-tests-fast run-bmark-tests-fast
update for rocket-chip release
2014-09-01 05:26:55 +02:00
first cut at parameter-based testing
2015-07-13 23:54:26 +02:00
.PHONY: run-asm-tests run-bmark-tests
.PHONY: run-asm-tests-debug run-bmark-tests-debug
.PHONY: run run-debug run-fast
update for rocket-chip release
2014-09-01 05:26:55 +02:00
junk += $(output_dir)
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