Add fragmenter in front of TLMemoryML507 and implementation notes

More than one core does not fit on the ml507 and is more than enough for
booting linux and executing basic utilities.

.gitmodules

@@ -1,9 +1,9 @@
 [submodule "rocket-chip"]
 	path = rocket-chip
-	url = https://github.com/ucb-bar/rocket-chip.git
+	url = https://git.tiband.de/riscv/rocket-chip.git
 [submodule "sifive-blocks"]
 	path = sifive-blocks
-	url = https://github.com/sifive/sifive-blocks.git
+	url = https://git.tiband.de/riscv/sifive-blocks.git
 [submodule "fpga-shells"]
 	path = fpga-shells
-	url = https://github.com/sifive/fpga-shells
+	url = https://git.tiband.de/riscv/fpga-shells.git

Makefile.u500ml507devkit

@@ -0,0 +1,24 @@
+# See LICENSE for license details.
+base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
+BUILD_DIR := $(base_dir)/builds/u500ml507devkit
+FPGA_DIR := $(base_dir)/fpga-shells/xilinx
+MODEL := U500ML507DevKitFPGAChip
+PROJECT := sifive.freedom.unleashed.u500ml507devkit
+export CONFIG_PROJECT := sifive.freedom.unleashed.u500ml507devkit
+export CONFIG := U500ML507DevKitConfig
+export BOARD := ml507
+export BOOTROM_DIR := $(base_dir)/bootrom/sdboot
+
+rocketchip_dir := $(base_dir)/rocket-chip
+sifiveblocks_dir := $(base_dir)/sifive-blocks
+VSRCS := \
+	$(rocketchip_dir)/vsrc/AsyncResetReg.v \
+	$(rocketchip_dir)/vsrc/plusarg_reader.v \
+	$(sifiveblocks_dir)/vsrc/SRLatch.v \
+	$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
+	$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
+	$(FPGA_DIR)/$(BOARD)/vsrc/ml507reset.v \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
+
+include common.mk

src/main/scala/unleashed/u500ml507devkit/Config.scala

@@ -0,0 +1,58 @@
+// See LICENSE for license details.
+package sifive.freedom.unleashed.u500ml507devkit
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.system._
+import freechips.rocketchip.tile._
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.terminal._
+
+import sifive.freedom.unleashed.u500ml507devkit.fpga._
+
+// Default FreedomUML507Config
+class FreedomUML507Config extends Config(
+  new WithoutTLMonitors      ++
+  new WithJtagDTM            ++
+  new WithNMemoryChannels(1) ++
+  new WithNBigCores(1)       ++
+  new BaseConfig
+)
+
+// Freedom U500 ML507 Dev Kit Peripherals
+class U500ML507DevKitPeripherals extends Config((site, here, up) => {
+  case PeripheryUARTKey => List(
+    UARTParams(address = BigInt(0x64000000L)))
+  case PeripherySPIKey => List(
+    SPIParams(rAddress = BigInt(0x64001000L)))
+  case PeripheryGPIOKey => List(
+    GPIOParams(address = BigInt(0x64002000L), width = 8))
+  case PeripheryTerminalKey =>
+    TerminalParams(address = BigInt(0x64003000L))
+  case PeripheryMaskROMKey => List(
+    MaskROMParams(address = 0x10000, name = "BootROM"))
+})
+
+// Freedom U500 ML507 Dev Kit
+class U500ML507DevKitConfig extends Config(
+  new WithNExtTopInterrupts(0)   ++
+  new U500ML507DevKitPeripherals ++
+  new FreedomUML507Config().alter((site,here,up) => {
+    case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128)
+    case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
+    case MemoryML507Key => MemoryML507Params(address = Seq(AddressSet(0x80000000L,0x10000000L-1))) // 256 MiB
+    case DTSTimebase => BigInt(1000000)
+    case ExtMem => up(ExtMem).copy(size = 0x40000000L)
+    case JtagDTMKey => new JtagDTMConfig (
+      idcodeVersion = 2,      // 1 was legacy (FE310-G000, Acai).
+      idcodePartNum = 0x000,  // Decided to simplify.
+      idcodeManufId = 0x489,  // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses.
+      debugIdleCycles = 5)    // Reasonable guess for synchronization
+  })
+)

src/main/scala/unleashed/u500ml507devkit/FPGAChip.scala

@@ -0,0 +1,65 @@
+// See LICENSE for license details.
+package sifive.freedom.unleashed.u500ml507devkit
+
+import Chisel._
+import chisel3.experimental.{withClockAndReset}
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.diplomacy._
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.pinctrl.{BasePin}
+
+import sifive.fpgashells.shell.xilinx.ml507shell._
+
+//-------------------------------------------------------------------------
+// PinGen
+//-------------------------------------------------------------------------
+
+object PinGen {
+  def apply(): BasePin = {
+    new BasePin()
+  }
+}
+
+//-------------------------------------------------------------------------
+// U500ML507DevKitFPGAChip
+//-------------------------------------------------------------------------
+
+class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
+    extends ML507Shell
+    with HasDebugJTAG {
+
+  //-----------------------------------------------------------------------
+  // DUT
+  //-----------------------------------------------------------------------
+
+  withClockAndReset(dut_clock, dut_reset) {
+    val dut = Module(LazyModule(new U500ML507DevKitSystem).module)
+
+    //---------------------------------------------------------------------
+    // Connect peripherals
+    //---------------------------------------------------------------------
+
+    connectTerminal (dut)
+    connectDebugJTAG(dut)
+    connectSPI      (dut)
+    connectUART     (dut)
+
+    //---------------------------------------------------------------------
+    // GPIO
+    //---------------------------------------------------------------------
+
+    val gpioParams = p(PeripheryGPIOKey)
+    val gpio_pins = Wire(new GPIOPins(() => PinGen(), gpioParams(0)))
+
+    GPIOPinsFromPort(gpio_pins, dut.gpio(0))
+
+    gpio_pins.pins.zipWithIndex.foreach {
+      case(pin, idx) =>
+        pin.i.ival := dip(idx)
+        led(idx) := pin.o.oval
+    }
+  }
+
+}

src/main/scala/unleashed/u500ml507devkit/System.scala

@@ -0,0 +1,47 @@
+// See LICENSE for license details.
+package sifive.freedom.unleashed.u500ml507devkit
+
+import Chisel._
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.system._
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.terminal._
+
+import sifive.freedom.unleashed.u500ml507devkit.fpga._
+
+//-------------------------------------------------------------------------
+// U500ML507DevKitSystem
+//-------------------------------------------------------------------------
+
+class U500ML507DevKitSystem(implicit p: Parameters) extends RocketSubsystem
+    with HasPeripheryMaskROMSlave
+    with HasPeripheryDebug
+    with HasSystemErrorSlave
+    with HasPeripheryUART
+    with HasPeripheryTerminal
+    with HasPeripherySPI
+    with HasPeripheryGPIO
+    with HasMemoryML507 {
+  override lazy val module = new U500ML507DevKitSystemModule(this)
+}
+
+class U500ML507DevKitSystemModule[+L <: U500ML507DevKitSystem](_outer: L)
+  extends RocketSubsystemModuleImp(_outer)
+    with HasRTCModuleImp
+    with HasPeripheryDebugModuleImp
+    with HasPeripheryUARTModuleImp
+    with HasPeripheryTerminalModuleImp
+    with HasPeripherySPIModuleImp
+    with HasPeripheryGPIOModuleImp {
+  // Reset vector is set to the location of the mask rom
+  val maskROMParams = p(PeripheryMaskROMKey)
+  global_reset_vector := maskROMParams(0).address.U
+}

src/main/scala/unleashed/u500ml507devkit/fpga/Memory.scala

@@ -0,0 +1,104 @@
+// See LICENSE.SiFive for license details.
+
+package sifive.freedom.unleashed.u500ml507devkit.fpga
+
+import Chisel._
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.subsystem.BaseSubsystem
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
+
+case class MemoryML507Params(
+    address: Seq[AddressSet]
+)
+
+case object MemoryML507Key extends Field[MemoryML507Params]
+
+trait HasMemoryML507 { this: BaseSubsystem =>
+    val memory = LazyModule(new TLMemoryML507(p(MemoryML507Key)))
+
+    // The Fragmenter will not fragment messages <= 32 bytes, so all
+    // slaves have to support this size. 64 byte specifies the maximum
+    // supported transfer size that the slave side of the fragmenter supports
+    // against the master (here the main memory bus). Specifying alwaysMin as
+    // true results in all messages being fragmented to the minimal size
+    // (32 byte). In TL1 terms, slaves
+    // correspond roughly to managers and masters to clients (confusingly…).
+    val fragmenter = TLFragmenter(32, 64, alwaysMin=true)
+
+    // TODO: right TL/memory node chain?
+    memory.node := fragmenter := memBuses.head.toDRAMController(Some("ml507mig"))()
+}
+
+class TLMemoryML507(c: MemoryML507Params)(implicit p: Parameters) extends LazyModule {
+    // Corresponds to MIG interface with 64 bit width and a burst length of 4
+    val width = 256
+    val beatBytes = width/8 // 32 byte (half a cache-line, fragmented)
+
+    val device = new MemoryDevice
+    val node = TLManagerNode(
+        Seq(TLManagerPortParameters(
+            Seq(TLManagerParameters(
+                address         = c.address,
+                resources       = device.reg,
+                regionType      = RegionType.UNCACHED,
+                executable      = true,
+                supportsGet     = TransferSizes(1, beatBytes),
+                supportsPutFull = TransferSizes(1, beatBytes),
+                fifoId          = Some(0) // in-order
+            )),
+            beatBytes = beatBytes
+        ))
+    )
+    // We could possibly also support supportsPutPartial, as we need support
+    // for masks anyway because of the possibility of transfers smaller that
+    // the data width (size signal, see below).
+
+    lazy val module = new LazyModuleImp(this) {
+        // in: TLBundle, edge: TLEdgeIn
+        val (in, edge) = node.in(0)
+
+        // Due to the Fragmenter defined above, all messages are 32 bytes or
+        // smaller. The data signal of the TL channels is also 32 bytes, so
+        // all messages will be transfered in a single beat.
+        // Also, TL guarantees (see TL$4.6) that the payload of a data message
+        // is always aligned to the width of the beat, e.g. in case of a 32
+        // byte data signal, data[7:0] will always have address 0x***00000 and
+        // data[255:247] address 0x***11111. It is also guaranteed that the
+        // mask bits always correctly reflect the active bytes inside the beat
+        // with respect to the size and address.
+        // So we can directly forward the mask, (relative) address and possibly
+        // data to the MIG interface.
+        // Put requests can be acknowledged as soon as they are latched into
+        // the write fifo of the MIG (possibly combinatorily).
+        // For read requests, we have to store the source id and size in a
+        // queue for later acknowledgment.
+        // We are ready if both the MIG and the response data queue are not
+        // full.
+
+        // Widths of the A channel:
+        // addressBits: 32
+        // dataBits:    256
+        // sourceBits:  6
+        // sinkBits:    1
+        // sizeBits:    3
+
+        // source (from): in.a.bits.source
+        // adresse (to): edgeIn.address(in.a.bits)
+        // size: edgeIn.size(in.a.bits)
+        // isPut: edgeIn.hasData(in.a.bits)
+
+        // bits kommt von Decoupled: ready, valid + bits
+
+        println("a parameters: " + in.a.bits.params)
+
+        in.a.ready := Bool(false)
+        in.d.valid := Bool(false)
+
+        // Tie off unused channels
+        in.b.valid := Bool(false)
+        in.c.ready := Bool(true)
+        in.e.ready := Bool(true)
+    }
+}