Wesley W. Terpstra
e1673b8670
README: note the vivado version requirements
2017-11-03 16:10:41 -07:00
Wesley W. Terpstra
4297b22472
unleashed: build quad-core instead
...
Because there are boot loaders out there that disable core 0, let's
make sure the open source design has >1 core to prevent these images
from hanging. We should also change freedom-u-sdk to check using DTS
to determine which cores to disable to properly fix this problem.
2017-11-03 16:10:41 -07:00
Wesley W. Terpstra
9f0877fc85
sdboot: support SMP boot
2017-11-03 16:10:41 -07:00
Wesley W. Terpstra
c965442560
u500: enable FPU; needed by linux
2017-11-03 16:10:41 -07:00
Wesley W. Terpstra
9cb03a3708
README: update location of built files
2017-11-03 16:10:41 -07:00
Wesley W. Terpstra
4eaac79ec2
freedom: bump submodules to their respective masters
2017-11-03 16:10:39 -07:00
Shreesha Srinath
22ee433699
README: Updates to build bootloaders
2017-08-20 01:39:45 -07:00
Shreesha Srinath
ec70d85cbc
Updates to Freedom SoCs
2017-08-18 23:51:07 -07:00
Richard Xia
f4375c2266
Add variable to control what program gets flashed to FPGA.
2016-12-08 12:14:17 -08:00
Wesley W. Terpstra
e95ae8aa31
README: our systems are untethered
2016-12-01 14:06:37 -08:00
Richard Xia
62d4e3ee15
Merge pull request #6 from sifive/remove-consts-vh
...
Remove verilog header files built from Chisel .prm file.
2016-12-01 11:05:18 -08:00
Richard Xia
db2128b4c2
Also remove unused .prm file from Makefile.
2016-11-30 15:00:50 -08:00
Richard Xia
c14985f3a7
Remove verilog header files built from Chisel .prm file.
2016-11-30 14:30:05 -08:00
Henry Styles
275e2cd693
Merge pull request #4 from sifive/fix_u500vc707devkit_dot_img
...
Update U500 VC707 Dev Kit BootROM image for SDBoot
2016-11-29 20:38:00 -08:00
Henry Styles
9fbf40da42
fix U500 BootROM image for SDBoot
2016-11-29 20:32:16 -08:00
Olof Kindgren
bf34011c03
Use public accessible URL for submodules
2016-11-29 14:30:01 -08:00
SiFive
32556462d0
Add submodules.
2016-11-29 05:23:27 -08:00
SiFive
3cf8128a30
Initial commit.
2016-11-29 05:23:11 -08:00
