riscv/freedom
1
0
Fork 0
Code Issues Releases Activity
SiFive Freedom platform (https://github.com/sifive/freedom)
6 Commits 3 Branches 0 Tags 1.1 MiB
Scala 56.9%
C 30.3%
Makefile 6.8%
Linker Script 4.5%
Assembly 0.9%
Other 0.6%
c14985f3a7
Go to file
Richard Xia c14985f3a7 Remove verilog header files built from Chisel .prm file.
2016-11-30 14:30:05 -08:00
bootrom fix U500 BootROM image for SDBoot 2016-11-29 20:32:16 -08:00
fpga Remove verilog header files built from Chisel .prm file. 2016-11-30 14:30:05 -08:00
rocket-chip@4146f6a792 Add submodules. 2016-11-29 05:23:27 -08:00
sifive-blocks@7916ef5249 Add submodules. 2016-11-29 05:23:27 -08:00
src/main/scala Initial commit. 2016-11-29 05:23:11 -08:00
.gitignore Initial commit. 2016-11-29 05:23:11 -08:00
.gitmodules Use public accessible URL for submodules 2016-11-29 14:30:01 -08:00
build.sbt Initial commit. 2016-11-29 05:23:11 -08:00
common.mk Remove verilog header files built from Chisel .prm file. 2016-11-30 14:30:05 -08:00
LICENSE Initial commit. 2016-11-29 05:23:11 -08:00
Makefile.e300artydevkit Initial commit. 2016-11-29 05:23:11 -08:00
Makefile.u500vc707devkit Initial commit. 2016-11-29 05:23:11 -08:00
README.md Initial commit. 2016-11-29 05:23:11 -08:00

README.md

Freedom

This repository contains the RTL created by SiFive for its Freedom E300 and U500 platforms. The Freedom E310 Arty FPGA Dev Kit implements the Freedom E300 Platform and is designed to be mapped onto an Arty FPGA Evaluation Kit. The Freedom U500 VC707 FPGA Dev Kit implements the Freedom U500 Platform and is designed to be mapped onto a VC707 FPGA Evaluation Kit.

Please read the section corresponding to the kit you are interested in for instructions on how to use this repo.

Freedom E310 Arty FPGA Dev Kit

The Freedom E310 Arty FPGA Dev Kit implements a Freedom E310 chip.

How to build

The Makefile corresponding to the Freedom E310 Arty FPGA Dev Kit is Makefile.e300artydevkit and it consists of two main targets:

  • verilog: to compile the Chisel source files and generate the Verilog files.
  • mcs: to create a Configuration Memory File (.mcs) that can be programmed onto an Arty FPGA board.

To execute these targets, you can run the following commands:

$ make -f Makefile.e300artydevkit verilog
$ make -f Makefile.e300artydevkit mcs

These will place the files under builds/e300artydevkit.

Note that in order to run the mcs target, you need to have the vivado executable on your PATH.

Bootrom

The default bootrom consists of a program that immediately jumps to address 0x20400000, which is 0x00400000 bytes into the SPI flash memory on the Arty board.

Freedom U500 VC707 FPGA Dev Kit

The Freedom U500 VC707 FPGA Dev Kit implements the Freedom U500 platform.

How to build

The Makefile corresponding to the Freedom U500 VC707 FPGA Dev Kit is Makefile.u500vc707devkit and it consists of two main targets:

  • verilog: to compile the Chisel source files and generate the Verilog files.
  • mcs: to create a Configuration Memory File (.mcs) that can be programmed onto an VC707 FPGA board.

To execute these targets, you can run the following commands:

$ make -f Makefile.u500vc707devkit verilog
$ make -f Makefile.u500vc707devkit mcs

These will place the files under builds/u500vc707devkit.

Note that in order to run the mcs target, you need to have the vivado executable on your PATH.

Bootrom

The default bootrom consists of a bootloader that loads a program off the SD card slot on the VC707 board.