riscv/fpga-shells
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Freedom FPGA mappings (https://github.com/sifive/fpga-shells)
62 Commits 2 Branches 0 Tags 682 KiB
Scala 89.5%
Tcl 7.8%
Verilog 2%
Makefile 0.7%
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Klemens Schölhorn 77694a6741 Add clock generation for the mig
2018-05-10 01:04:52 +02:00
src/main/scala Add clock generation for the mig 2018-05-10 01:04:52 +02:00
xilinx prologue: support the absence of an xdc/tcl constraint file 2018-02-25 15:21:03 -08:00
.gitignore Initial commit for fpga-shells 2017-08-16 11:23:45 -07:00