 Henry Styles
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61b167e8d9
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VC707 : use IO bundles directly from the PCIe and MIG devices instead of redeclaring signals
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2017-10-23 16:53:59 -07:00 |
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  Wesley W. TerpstraandGitHub
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d8e50c7646
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TLToAXI4: remove now unnecessary argument (#10)
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2017-10-12 14:37:21 -07:00 |
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Wesley W. TerpstraandGitHub
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4af0552374
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diplomacy: update to new API (#7)
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2017-09-27 16:32:43 -07:00 |
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 Megan Wachs
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bf48e2c7c4
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signal_bundles: Use the new way as .fromPorts is gone
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2017-09-22 13:31:11 -07:00 |
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Henry Styles
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9f75e6eb59
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Support both 4G and 1GB DIMM configuration for VC707
Generate IP TCL and MIG projects from the Chisel blackboxes
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2017-09-08 15:52:53 -07:00 |
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Megan Wachs
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13671f906d
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synchronizers: Use new primitives
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2017-09-06 11:00:25 -07:00 |
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 Shreesha Srinath
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2389e6e957
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Fix the package path for xilinx vc707mig
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2017-08-18 14:47:03 -07:00 |
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Shreesha Srinath
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c58e79f155
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vc707: Updates to the constraints and shell
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2017-08-17 18:51:01 -07:00 |
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Shreesha Srinath
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ab8cf0775f
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Initial commit for fpga-shells
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2017-08-16 11:23:45 -07:00 |
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