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Commit Graph

8 Commits

Author SHA1 Message Date
Henry Styles
dc6bb40d1b VC707 : update contraints file to match PCIe and MIG signal names now claimed directly from the IP 2017-10-23 17:27:36 -07:00
Henry Styles
9f75e6eb59 Support both 4G and 1GB DIMM configuration for VC707
Generate IP TCL and MIG projects from the Chisel blackboxes
2017-09-08 15:52:53 -07:00
Megan Wachs
31650a2d23 Merge remote-tracking branch 'origin/master' into synchronizers 2017-09-07 10:46:03 -07:00
Henry Styles
b7ee0ab0f0 fix PCIe vc707 design contraints : PCIe pins and UART RX sync register 2017-09-07 10:41:12 -07:00
Megan Wachs
cab572fab2 synchronizers: decided that ShiftRegInit should be reversed as the others. 2017-09-07 09:54:35 -07:00
Megan Wachs
fd70d118d3 synchronizers: Update constraints to match new hierarchy for synchronizers 2017-09-07 07:50:22 -07:00
Shreesha Srinath
c58e79f155 vc707: Updates to the constraints and shell 2017-08-17 18:51:01 -07:00
Shreesha Srinath
ab8cf0775f Initial commit for fpga-shells 2017-08-16 11:23:45 -07:00