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0ca9f2bb66
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periphery: bus api update (#17)
* periphery: bus api update
* Update XilinxVC707MIGPeriphery.scala
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2018-03-01 01:16:04 -08:00 |
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df8e6b8e8c
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xilinxvc707pciex1: use new node-style API and abstract crossing (#13)
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2017-10-28 12:27:24 -07:00 |
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65ac5d4588
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xilinxVC707mig: convert to the island pattern (#12)
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2017-10-26 16:38:52 -07:00 |
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61b167e8d9
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VC707 : use IO bundles directly from the PCIe and MIG devices instead of redeclaring signals
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2017-10-23 16:53:59 -07:00 |
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d8e50c7646
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TLToAXI4: remove now unnecessary argument (#10)
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2017-10-12 14:37:21 -07:00 |
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4af0552374
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diplomacy: update to new API (#7)
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2017-09-27 16:32:43 -07:00 |
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ab8cf0775f
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Initial commit for fpga-shells
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2017-08-16 11:23:45 -07:00 |
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