77 lines
2.3 KiB
Scala
77 lines
2.3 KiB
Scala
// See LICENSE for license details.
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package sifive.fpgashells.devices.xilinx.xilinxvc707pciex1
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import Chisel._
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import freechips.rocketchip.amba.axi4._
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import freechips.rocketchip.coreplex.CacheBlockBytes
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import freechips.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import sifive.fpgashells.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
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import sifive.fpgashells.ip.xilinx.ibufds_gte2.IBUFDS_GTE2
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class XilinxVC707PCIeX1Pads extends Bundle with VC707AXIToPCIeX1IOSerial
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class XilinxVC707PCIeX1IO extends Bundle
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with VC707AXIToPCIeX1IOSerial
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with VC707AXIToPCIeX1IOClocksReset {
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val axi_ctl_aresetn = Bool(INPUT)
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val REFCLK_rxp = Bool(INPUT)
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val REFCLK_rxn = Bool(INPUT)
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}
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class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
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val slave = TLAsyncInputNode()
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val control = TLAsyncInputNode()
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val master = TLAsyncOutputNode()
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val intnode = IntOutputNode()
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val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
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axi_to_pcie_x1.slave :=
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AXI4Buffer()(
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AXI4UserYanker()(
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AXI4Deinterleaver(p(CacheBlockBytes))(
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AXI4IdIndexer(idBits=4)(
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TLToAXI4(beatBytes=8, adapterName = Some("pcie-slave"))(
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TLAsyncCrossingSink()(
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slave))))))
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axi_to_pcie_x1.control :=
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AXI4Buffer()(
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AXI4UserYanker(capMaxFlight = Some(2))(
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TLToAXI4(beatBytes=4)(
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TLFragmenter(4, p(CacheBlockBytes))(
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TLAsyncCrossingSink()(
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control)))))
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master :=
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TLAsyncCrossingSource()(
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TLWidthWidget(8)(
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AXI4ToTL()(
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AXI4UserYanker(capMaxFlight=Some(8))(
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AXI4Fragmenter()(
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axi_to_pcie_x1.master)))))
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intnode := axi_to_pcie_x1.intnode
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val port = new XilinxVC707PCIeX1IO
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val slave_in = slave.bundleIn
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val control_in = control.bundleIn
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val master_out = master.bundleOut
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val interrupt = intnode.bundleOut
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}
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io.port <> axi_to_pcie_x1.module.io.port
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//PCIe Reference Clock
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val ibufds_gte2 = Module(new IBUFDS_GTE2)
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axi_to_pcie_x1.module.io.REFCLK := ibufds_gte2.io.O
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ibufds_gte2.io.CEB := UInt(0)
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ibufds_gte2.io.I := io.port.REFCLK_rxp
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ibufds_gte2.io.IB := io.port.REFCLK_rxn
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}
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}
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