From f9dc552ddc6144c613a3e6cc5d5c44aea3b3dcc4 Mon Sep 17 00:00:00 2001 From: Henry Styles Date: Wed, 10 Jan 2018 14:23:50 -0800 Subject: [PATCH] Xilinx unisim typo --- src/main/scala/ip/xilinx/Unisim.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/ip/xilinx/Unisim.scala b/src/main/scala/ip/xilinx/Unisim.scala index 89842b0..f781780 100644 --- a/src/main/scala/ip/xilinx/Unisim.scala +++ b/src/main/scala/ip/xilinx/Unisim.scala @@ -33,7 +33,7 @@ extends BlackBox( "DIFF_TERM" -> booleanToVerilogStringParam(DIFF_TERM), "DQS_BIAS" -> booleanToVerilogStringParam(DQS_BIAS), "IBUF_DELAY_VALUE" -> IntParam(IBUF_DELAY_VALUE), - "IBUDF_LOW_PWR" -> booleanToVerilogStringParam(IBUF_LOW_PWR), + "IBUF_LOW_PWR" -> booleanToVerilogStringParam(IBUF_LOW_PWR), "IFD_DELAY_VALUE" -> StringParam(IFD_DELAY_VALUE), "IOSTANDARD" -> StringParam(IOSTANDARD) )