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Merge pull request #1 from sifive/synchronizers

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synchronizers: Use new primitives
This commit is contained in:
Megan Wachs 2017-09-07 13:33:26 -07:00 committed by GitHub
commit e49f49686d
2 changed files with 3 additions and 6 deletions
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7
src/main/scala/shell/xilinx/VC707Shell.scala
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@ -7,11 +7,11 @@ import chisel3.experimental.{RawModule, Analog, withClockAndReset}
import freechips.rocketchip.config._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.util.{SyncResetSynchronizerShiftReg}
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.blocks.util.{ShiftRegister}
import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
@ -201,11 +201,8 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule {
def connectUART(dut: HasPeripheryUARTModuleImp): Unit = {
val uartParams = p(PeripheryUARTKey)
if (!uartParams.isEmpty) {
// synchronize uart_rx
val uart_rx_sync = ShiftRegister(uart_rx, 2, true.B, ~dut.reset, name=Some("uart_rx"))
// uart connections
dut.uart(0).rxd := uart_rx_sync
dut.uart(0).rxd := SyncResetSynchronizerShiftReg(uart_rx, 2, init = Bool(true), name=Some("uart_rxd_sync"))
uart_tx := dut.uart(0).txd
}
}

2
xilinx/vc707/constraints/vc707-master.xdc
View File

@ -31,7 +31,7 @@ set_property IOB TRUE [get_ports uart_rtsn]
# Platform specific constraints
set_property IOB TRUE [get_cells "U500VC707System/uarts_0/txm/out_reg"]
set_property IOB TRUE [get_cells "uart_rx_sync_0_reg"]
set_property IOB TRUE [get_cells "uart_rxd_sync/sync_1"]
# PCI Express
#FMC 1 refclk