From 13671f906d8e0f2b925fd5e998a34da480256143 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Wed, 6 Sep 2017 11:00:25 -0700 Subject: [PATCH 1/3] synchronizers: Use new primitives --- src/main/scala/shell/xilinx/VC707Shell.scala | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/main/scala/shell/xilinx/VC707Shell.scala b/src/main/scala/shell/xilinx/VC707Shell.scala index d11f7a8..b3b1a58 100644 --- a/src/main/scala/shell/xilinx/VC707Shell.scala +++ b/src/main/scala/shell/xilinx/VC707Shell.scala @@ -7,11 +7,11 @@ import chisel3.experimental.{RawModule, Analog, withClockAndReset} import freechips.rocketchip.config._ import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.util.{SyncResetSynchronizerShiftReg} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.uart._ -import sifive.blocks.util.{ShiftRegister} import sifive.fpgashells.devices.xilinx.xilinxvc707mig._ import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._ @@ -201,11 +201,8 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule { def connectUART(dut: HasPeripheryUARTModuleImp): Unit = { val uartParams = p(PeripheryUARTKey) if (!uartParams.isEmpty) { - // synchronize uart_rx - val uart_rx_sync = ShiftRegister(uart_rx, 2, true.B, ~dut.reset, name=Some("uart_rx")) - // uart connections - dut.uart(0).rxd := uart_rx_sync + dut.uart(0).rxd := SyncResetSynchronizerShiftReg(uart_rx, 2, init = Bool(true), name=Some("uart_rxd_sync")) uart_tx := dut.uart(0).txd } } From fd70d118d38c3c060acf5fbe58fb184d4148c82c Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Thu, 7 Sep 2017 07:46:21 -0700 Subject: [PATCH 2/3] synchronizers: Update constraints to match new hierarchy for synchronizers --- xilinx/vc707/constraints/vc707-master.xdc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xilinx/vc707/constraints/vc707-master.xdc b/xilinx/vc707/constraints/vc707-master.xdc index 608a358..f6b11a7 100644 --- a/xilinx/vc707/constraints/vc707-master.xdc +++ b/xilinx/vc707/constraints/vc707-master.xdc @@ -31,7 +31,7 @@ set_property IOB TRUE [get_ports uart_rtsn] # Platform specific constraints set_property IOB TRUE [get_cells "U500VC707System/uarts_0/txm/out_reg"] -set_property IOB TRUE [get_cells "uart_rx_sync_0"] +set_property IOB TRUE [get_cells "uart_rxd_sync/sync_0"] # PCI Express #FMC 1 refclk From cab572fab2bd35a11ba90d94dfce6325d37ac241 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Thu, 7 Sep 2017 09:54:35 -0700 Subject: [PATCH 3/3] synchronizers: decided that ShiftRegInit should be reversed as the others. --- xilinx/vc707/constraints/vc707-master.xdc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xilinx/vc707/constraints/vc707-master.xdc b/xilinx/vc707/constraints/vc707-master.xdc index f6b11a7..5774ffc 100644 --- a/xilinx/vc707/constraints/vc707-master.xdc +++ b/xilinx/vc707/constraints/vc707-master.xdc @@ -31,7 +31,7 @@ set_property IOB TRUE [get_ports uart_rtsn] # Platform specific constraints set_property IOB TRUE [get_cells "U500VC707System/uarts_0/txm/out_reg"] -set_property IOB TRUE [get_cells "uart_rxd_sync/sync_0"] +set_property IOB TRUE [get_cells "uart_rxd_sync/sync_1"] # PCI Express #FMC 1 refclk