TLToAXI4: remove now unnecessary argument (#10)
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@ -41,7 +41,7 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
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beatBytes = 8)))
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beatBytes = 8)))
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val xing = LazyModule(new TLAsyncCrossing)
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val xing = LazyModule(new TLAsyncCrossing)
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val toaxi4 = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
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val toaxi4 = LazyModule(new TLToAXI4(adapterName = Some("mem"), stripBits = 1))
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val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
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val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
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val deint = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
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val deint = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
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val yank = LazyModule(new AXI4UserYanker)
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val yank = LazyModule(new AXI4UserYanker)
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@ -33,14 +33,14 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
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AXI4UserYanker()(
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AXI4UserYanker()(
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AXI4Deinterleaver(p(CacheBlockBytes))(
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AXI4Deinterleaver(p(CacheBlockBytes))(
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AXI4IdIndexer(idBits=4)(
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AXI4IdIndexer(idBits=4)(
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TLToAXI4(beatBytes=8, adapterName = Some("pcie-slave"))(
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TLToAXI4(adapterName = Some("pcie-slave"))(
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TLAsyncCrossingSink()(
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TLAsyncCrossingSink()(
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slave))))))
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slave))))))
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axi_to_pcie_x1.control :=
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axi_to_pcie_x1.control :=
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AXI4Buffer()(
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AXI4Buffer()(
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AXI4UserYanker(capMaxFlight = Some(2))(
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AXI4UserYanker(capMaxFlight = Some(2))(
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TLToAXI4(beatBytes=4)(
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TLToAXI4()(
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TLFragmenter(4, p(CacheBlockBytes))(
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TLFragmenter(4, p(CacheBlockBytes))(
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TLAsyncCrossingSink()(
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TLAsyncCrossingSink()(
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control)))))
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control)))))
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