diff --git a/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala
index fe093de..f79a558 100644
--- a/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala
@@ -41,7 +41,7 @@ class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends L
     beatBytes = 8)))
 
   val xing    = LazyModule(new TLAsyncCrossing)
-  val toaxi4  = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
+  val toaxi4  = LazyModule(new TLToAXI4(adapterName = Some("mem"), stripBits = 1))
   val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
   val deint   = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
   val yank    = LazyModule(new AXI4UserYanker)
diff --git a/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala b/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
index 1dbea70..8d27178 100644
--- a/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
+++ b/src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
@@ -33,14 +33,14 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
     AXI4UserYanker()(
     AXI4Deinterleaver(p(CacheBlockBytes))(
     AXI4IdIndexer(idBits=4)(
-    TLToAXI4(beatBytes=8, adapterName = Some("pcie-slave"))(
+    TLToAXI4(adapterName = Some("pcie-slave"))(
     TLAsyncCrossingSink()(
     slave))))))
 
   axi_to_pcie_x1.control :=
     AXI4Buffer()(
     AXI4UserYanker(capMaxFlight = Some(2))(
-    TLToAXI4(beatBytes=4)(
+    TLToAXI4()(
     TLFragmenter(4, p(CacheBlockBytes))(
     TLAsyncCrossingSink()(
     control)))))