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vc707: setup 100MHz PLL

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Wesley W. Terpstra committed 2018-02-08 07:21:45 -08:00
1 parent 506d2da883
commit 8519ba8d4e
3 files changed
+30 -27
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xilinx/vc707/constraints/vc707-master.xdc
+6 -1
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@@ -72,9 +72,12 @@ set_property -dict { PACKAGE_PIN AU31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRU
set_property -dict { PACKAGE_PIN AV31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[2]}]
set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[3]}]
create_clock -name chiplink_b2c_clock -period 10 [get_ports chiplink_b2c_clk]
set_clock_groups -asynchronous \
-group { clk_pll_i } \
-group { \
sys_diff_clk \
clk_out1_vc707_sys_clock_mmcm2 \
clk_out2_vc707_sys_clock_mmcm2 \
clk_out3_vc707_sys_clock_mmcm2 \
@@ -85,5 +88,7 @@ set_clock_groups -asynchronous \
-group { \
clk_out1_vc707_sys_clock_mmcm1 \
clk_out2_vc707_sys_clock_mmcm1 } \
-group { \
clk_out1_vc707_sys_clock_mmcm3 \
chiplink_b2c_clock } \
-group [list [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]]]