From 8519ba8d4e02b21875f2828fa0f43f425fc370c4 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Wed, 24 Jan 2018 17:27:29 -0800 Subject: [PATCH] vc707: setup 100MHz PLL --- src/main/scala/ip/xilinx/Xilinx.scala | 48 ++++++++++---------- src/main/scala/shell/xilinx/VC707Shell.scala | 2 +- xilinx/vc707/constraints/vc707-master.xdc | 7 ++- 3 files changed, 30 insertions(+), 27 deletions(-) diff --git a/src/main/scala/ip/xilinx/Xilinx.scala b/src/main/scala/ip/xilinx/Xilinx.scala index 9d90046..db8a965 100644 --- a/src/main/scala/ip/xilinx/Xilinx.scala +++ b/src/main/scala/ip/xilinx/Xilinx.scala @@ -243,7 +243,7 @@ class vc707_sys_clock_mmcm2 extends BlackBox { CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {50} \ CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {100} \ CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {150.000} \ - CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {12.5} \ + CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {100} \ CONFIG.CLKOUT7_REQUESTED_PHASE {180} \ CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ CONFIG.PRIM_IN_FREQ {200.000} \ @@ -257,22 +257,22 @@ class vc707_sys_clock_mmcm2 extends BlackBox { CONFIG.MMCM_CLKOUT3_DIVIDE {18} \ CONFIG.MMCM_CLKOUT4_DIVIDE {9} \ CONFIG.MMCM_CLKOUT5_DIVIDE {6} \ - CONFIG.MMCM_CLKOUT6_DIVIDE {72} \ + CONFIG.MMCM_CLKOUT6_DIVIDE {9} \ CONFIG.NUM_OUT_CLKS {7} \ CONFIG.CLKOUT1_JITTER {206.010} \ CONFIG.CLKOUT1_PHASE_ERROR {105.461} \ CONFIG.CLKOUT2_JITTER {180.172} \ CONFIG.CLKOUT2_PHASE_ERROR {105.461} \ CONFIG.CLKOUT3_JITTER {166.503} \ - CONFIG.CLKOUT3_PHASE_ERROR {105.503} \ + CONFIG.CLKOUT3_PHASE_ERROR {105.461} \ CONFIG.CLKOUT4_JITTER {157.199} \ CONFIG.CLKOUT4_PHASE_ERROR {105.461} \ - CONFIG.CLKOUT5_JITTER {110.629} \ - CONFIG.CLKOUT5_PHASE_ERROR {136.686} \ + CONFIG.CLKOUT5_JITTER {136.686} \ + CONFIG.CLKOUT5_PHASE_ERROR {105.461} \ CONFIG.CLKOUT6_JITTER {126.399} \ CONFIG.CLKOUT6_PHASE_ERROR {105.461} \ CONFIG.CLKOUT7_JITTER {206.010} \ - CONFIG.CLKOUT7_PHASE_ERROR {105.461}] [get_ips vc707_sys_clock_mmcm2] """ + CONFIG.CLKOUT7_PHASE_ERROR {136.686}] [get_ips vc707_sys_clock_mmcm2] """ ) } @@ -280,31 +280,29 @@ class vc707_sys_clock_mmcm3 extends BlackBox { val io = new Bundle { val clk_in1 = Bool(INPUT) val clk_out1 = Clock(OUTPUT) - val clk_out2 = Clock(OUTPUT) val reset = Bool(INPUT) val locked = Bool(OUTPUT) } - + ElaborationArtefacts.add( "vc707_sys_clock_mmcm3.vivado.tcl", """create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name vc707_sys_clock_mmcm3 -dir $ipdir -force - set_property -dict [list CONFIG.PRIM_IN_FREQ {12.5} \ - CONFIG.CLKOUT2_USED {true} \ - CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.5} \ - CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {12.5} \ - CONFIG.CLKOUT2_REQUESTED_PHASE {180} \ - CONFIG.CLKIN1_JITTER_PS {800.0} \ - CONFIG.MMCM_DIVCLK_DIVIDE {1} \ - CONFIG.MMCM_CLKFBOUT_MULT_F {64.000} \ - CONFIG.MMCM_CLKIN1_PERIOD {80.0} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {64.000} \ - CONFIG.MMCM_CLKOUT1_DIVIDE {64} \ - CONFIG.MMCM_CLKOUT1_PHASE {180.000} \ - CONFIG.NUM_OUT_CLKS {2} \ - CONFIG.CLKOUT1_JITTER {627.393} \ - CONFIG.CLKOUT1_PHASE_ERROR {651.718} \ - CONFIG.CLKOUT2_JITTER {627.393} \ - CONFIG.CLKOUT2_PHASE_ERROR {651.718}] [get_ips vc707_sys_clock_mmcm3] """ + set_property -dict [list \ + CONFIG.PRIM_SOURCE {No_buffer} \ + CONFIG.PRIM_IN_FREQ {100} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100} \ + CONFIG.CLKOUT1_REQUESTED_PHASE {180} \ + CONFIG.CLK_IN1_BOARD_INTERFACE {Custom} \ + CONFIG.CLKIN1_JITTER_PS {100.0} \ + CONFIG.MMCM_DIVCLK_DIVIDE {1} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {10.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {10.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {10} \ + CONFIG.MMCM_CLKOUT1_PHASE {180.000} \ + CONFIG.NUM_OUT_CLKS {1} \ + CONFIG.CLKOUT1_JITTER {130.958} \ + CONFIG.CLKOUT1_PHASE_ERROR {98.575}] [get_ips vc707_sys_clock_mmcm3] """ ) } diff --git a/src/main/scala/shell/xilinx/VC707Shell.scala b/src/main/scala/shell/xilinx/VC707Shell.scala index fb2e64b..5832df6 100644 --- a/src/main/scala/shell/xilinx/VC707Shell.scala +++ b/src/main/scala/shell/xilinx/VC707Shell.scala @@ -233,7 +233,7 @@ abstract class VC707Shell(implicit val p: Parameters) extends RawModule { val clk100 = vc707_sys_clock_mmcm0.io.clk_out5 val clk150 = vc707_sys_clock_mmcm0.io.clk_out6 val clk75 = vc707_sys_clock_mmcm0.io.clk_out7 - val clk12_5_180 = vc707_sys_clock_mmcm0.io.clk_out7 + val clk100_180 = vc707_sys_clock_mmcm0.io.clk_out7 val vc707_sys_clock_mmcm0_locked = vc707_sys_clock_mmcm0.io.locked //65MHz and multiples diff --git a/xilinx/vc707/constraints/vc707-master.xdc b/xilinx/vc707/constraints/vc707-master.xdc index 76d6d81..1580231 100644 --- a/xilinx/vc707/constraints/vc707-master.xdc +++ b/xilinx/vc707/constraints/vc707-master.xdc @@ -72,9 +72,12 @@ set_property -dict { PACKAGE_PIN AU31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRU set_property -dict { PACKAGE_PIN AV31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[2]}] set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[3]}] +create_clock -name chiplink_b2c_clock -period 10 [get_ports chiplink_b2c_clk] + set_clock_groups -asynchronous \ -group { clk_pll_i } \ -group { \ + sys_diff_clk \ clk_out1_vc707_sys_clock_mmcm2 \ clk_out2_vc707_sys_clock_mmcm2 \ clk_out3_vc707_sys_clock_mmcm2 \ @@ -85,5 +88,7 @@ set_clock_groups -asynchronous \ -group { \ clk_out1_vc707_sys_clock_mmcm1 \ clk_out2_vc707_sys_clock_mmcm1 } \ + -group { \ + clk_out1_vc707_sys_clock_mmcm3 \ + chiplink_b2c_clock } \ -group [list [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]]] -