riscv/fpga-shells
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Fix memory controller signal name

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This commit is contained in:
Klemens Schölhorn
2018-05-10 02:27:31 +02:00
parent 77694a6741
commit 7e53be49f9
1 changed files with 1 additions and 1 deletions
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src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala
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@ -20,7 +20,7 @@ class MemoryController extends BlackBox {
val ddr2 = new MemoryDDR2IO val ddr2 = new MemoryDDR2IO
val request_addr = Input(UInt(28.W)) val request_addr = Input(UInt(28.W))
val request_read = Input(Bool()) val request_type = Input(Bool())
val request_data = Input(UInt(256.W)) val request_data = Input(UInt(256.W))
val request_mask = Input(UInt(32.W)) val request_mask = Input(UInt(32.W))
val request_valid = Input(Bool()) val request_valid = Input(Bool())