From 7e53be49f92eed95c8a3c0124ccc3677d7d9f5b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Klemens=20Sch=C3=B6lhorn?= Date: Thu, 10 May 2018 02:27:31 +0200 Subject: [PATCH] Fix memory controller signal name --- .../scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala b/src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala index e9a7088..96637f2 100644 --- a/src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala +++ b/src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala @@ -20,7 +20,7 @@ class MemoryController extends BlackBox { val ddr2 = new MemoryDDR2IO val request_addr = Input(UInt(28.W)) - val request_read = Input(Bool()) + val request_type = Input(Bool()) val request_data = Input(UInt(256.W)) val request_mask = Input(UInt(32.W)) val request_valid = Input(Bool())