Merge pull request #18 from sifive/dynamic-clock-groups
Dynamic clock groups -- fixes timing closure problem for vc707 designs without ChipLink
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commit
6df6db25de
@ -115,4 +115,5 @@ if {[get_filesets -quiet constrs_1] eq ""} {
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}
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}
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set obj [current_fileset -constrset]
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set obj [current_fileset -constrset]
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add_files -norecurse -fileset $obj [glob -directory $constraintsdir {*.xdc}]
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add_files -norecurse -fileset $obj [glob -directory $constraintsdir -nocomplain {*.xdc}]
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add_files -norecurse -fileset $obj [glob -directory $constraintsdir -nocomplain {*.tcl}]
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25
xilinx/vc707/constraints/vc707-master.tcl
Normal file
25
xilinx/vc707/constraints/vc707-master.tcl
Normal file
@ -0,0 +1,25 @@
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if { [llength [get_ports -quiet chiplink_b2c_clk]] > 0 } {
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create_clock -name chiplink_b2c_clock -period 10 [get_ports chiplink_b2c_clk]
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}
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set group_mem [get_clocks -quiet {clk_pll_i}]
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set group_sys [get_clocks -quiet {sys_diff_clk \
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clk_out*_vc707_sys_clock_mmcm1 \
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clk_out*_vc707_sys_clock_mmcm2}]
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set group_cl [get_clocks -quiet {chiplink_b2c_clock \
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clk_out*_vc707_sys_clock_mmcm3}]
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set group_pci [get_clocks -quiet -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]]
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puts "group_mem: $group_mem"
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puts "group_sys: $group_sys"
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puts "group_pci: $group_pci"
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puts "group_cl: $group_cl"
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set groups [list]
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if { [llength $group_mem] > 0 } { lappend groups -group $group_mem }
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if { [llength $group_sys] > 0 } { lappend groups -group $group_sys }
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if { [llength $group_pci] > 0 } { lappend groups -group $group_pci }
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if { [llength $group_cl] > 0 } { lappend groups -group $group_cl }
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puts "set_clock_groups -asynchronous $groups"
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set_clock_groups -asynchronous {*}$groups
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@ -71,24 +71,3 @@ set_property -dict { PACKAGE_PIN AR30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRU
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set_property -dict { PACKAGE_PIN AU31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[1]}]
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set_property -dict { PACKAGE_PIN AU31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[1]}]
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set_property -dict { PACKAGE_PIN AV31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[2]}]
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set_property -dict { PACKAGE_PIN AV31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[2]}]
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set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[3]}]
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set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[3]}]
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create_clock -name chiplink_b2c_clock -period 10 [get_ports chiplink_b2c_clk]
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set_clock_groups -asynchronous \
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-group { clk_pll_i } \
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-group { \
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sys_diff_clk \
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clk_out1_vc707_sys_clock_mmcm2 \
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clk_out2_vc707_sys_clock_mmcm2 \
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clk_out3_vc707_sys_clock_mmcm2 \
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clk_out4_vc707_sys_clock_mmcm2 \
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clk_out5_vc707_sys_clock_mmcm2 \
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clk_out6_vc707_sys_clock_mmcm2 \
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clk_out7_vc707_sys_clock_mmcm2 } \
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-group { \
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clk_out1_vc707_sys_clock_mmcm1 \
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clk_out2_vc707_sys_clock_mmcm1 } \
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-group { \
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clk_out1_vc707_sys_clock_mmcm3 \
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chiplink_b2c_clock } \
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-group [list [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]]]
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