From b7afc83a34c54af35b817be2709ed0215b5c1b43 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sun, 25 Feb 2018 14:32:39 -0800 Subject: [PATCH 1/2] xilinx prologue: support tcl for constraints --- xilinx/common/tcl/prologue.tcl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/xilinx/common/tcl/prologue.tcl b/xilinx/common/tcl/prologue.tcl index 3476b04..dbee383 100644 --- a/xilinx/common/tcl/prologue.tcl +++ b/xilinx/common/tcl/prologue.tcl @@ -115,4 +115,5 @@ if {[get_filesets -quiet constrs_1] eq ""} { } set obj [current_fileset -constrset] -add_files -norecurse -fileset $obj [glob -directory $constraintsdir {*.xdc}] +add_files -norecurse -fileset $obj [glob -directory $constraintsdir -nocomplain {*.xdc}] +add_files -norecurse -fileset $obj [glob -directory $constraintsdir -nocomplain {*.tcl}] From 438618701660d115ec5e377bc8d4d0c85caa62b3 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Sun, 25 Feb 2018 14:33:32 -0800 Subject: [PATCH 2/2] vc707: add clock groups dynamically iff they exist --- xilinx/vc707/constraints/vc707-master.tcl | 25 +++++++++++++++++++++++ xilinx/vc707/constraints/vc707-master.xdc | 21 ------------------- 2 files changed, 25 insertions(+), 21 deletions(-) create mode 100644 xilinx/vc707/constraints/vc707-master.tcl diff --git a/xilinx/vc707/constraints/vc707-master.tcl b/xilinx/vc707/constraints/vc707-master.tcl new file mode 100644 index 0000000..b5bb61f --- /dev/null +++ b/xilinx/vc707/constraints/vc707-master.tcl @@ -0,0 +1,25 @@ +if { [llength [get_ports -quiet chiplink_b2c_clk]] > 0 } { + create_clock -name chiplink_b2c_clock -period 10 [get_ports chiplink_b2c_clk] +} + +set group_mem [get_clocks -quiet {clk_pll_i}] +set group_sys [get_clocks -quiet {sys_diff_clk \ + clk_out*_vc707_sys_clock_mmcm1 \ + clk_out*_vc707_sys_clock_mmcm2}] +set group_cl [get_clocks -quiet {chiplink_b2c_clock \ + clk_out*_vc707_sys_clock_mmcm3}] +set group_pci [get_clocks -quiet -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]] + +puts "group_mem: $group_mem" +puts "group_sys: $group_sys" +puts "group_pci: $group_pci" +puts "group_cl: $group_cl" + +set groups [list] +if { [llength $group_mem] > 0 } { lappend groups -group $group_mem } +if { [llength $group_sys] > 0 } { lappend groups -group $group_sys } +if { [llength $group_pci] > 0 } { lappend groups -group $group_pci } +if { [llength $group_cl] > 0 } { lappend groups -group $group_cl } + +puts "set_clock_groups -asynchronous $groups" +set_clock_groups -asynchronous {*}$groups diff --git a/xilinx/vc707/constraints/vc707-master.xdc b/xilinx/vc707/constraints/vc707-master.xdc index 1580231..d99801f 100644 --- a/xilinx/vc707/constraints/vc707-master.xdc +++ b/xilinx/vc707/constraints/vc707-master.xdc @@ -71,24 +71,3 @@ set_property -dict { PACKAGE_PIN AR30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRU set_property -dict { PACKAGE_PIN AU31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[1]}] set_property -dict { PACKAGE_PIN AV31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[2]}] set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[3]}] - -create_clock -name chiplink_b2c_clock -period 10 [get_ports chiplink_b2c_clk] - -set_clock_groups -asynchronous \ - -group { clk_pll_i } \ - -group { \ - sys_diff_clk \ - clk_out1_vc707_sys_clock_mmcm2 \ - clk_out2_vc707_sys_clock_mmcm2 \ - clk_out3_vc707_sys_clock_mmcm2 \ - clk_out4_vc707_sys_clock_mmcm2 \ - clk_out5_vc707_sys_clock_mmcm2 \ - clk_out6_vc707_sys_clock_mmcm2 \ - clk_out7_vc707_sys_clock_mmcm2 } \ - -group { \ - clk_out1_vc707_sys_clock_mmcm1 \ - clk_out2_vc707_sys_clock_mmcm1 } \ - -group { \ - clk_out1_vc707_sys_clock_mmcm3 \ - chiplink_b2c_clock } \ - -group [list [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]]]