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Merge pull request #18 from sifive/dynamic-clock-groups

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Dynamic clock groups -- fixes timing closure problem for vc707 designs without ChipLink
This commit is contained in:
Wesley W. Terpstra 2018-02-25 15:08:15 -08:00 committed by GitHub
commit 6df6db25de
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 27 additions and 22 deletions
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3
xilinx/common/tcl/prologue.tcl
View File

@ -115,4 +115,5 @@ if {[get_filesets -quiet constrs_1] eq ""} {
} }
set obj [current_fileset -constrset] set obj [current_fileset -constrset]
add_files -norecurse -fileset $obj [glob -directory $constraintsdir {*.xdc}] add_files -norecurse -fileset $obj [glob -directory $constraintsdir -nocomplain {*.xdc}]
add_files -norecurse -fileset $obj [glob -directory $constraintsdir -nocomplain {*.tcl}]

25
xilinx/vc707/constraints/vc707-master.tcl Normal file
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@ -0,0 +1,25 @@
if { [llength [get_ports -quiet chiplink_b2c_clk]] > 0 } {
create_clock -name chiplink_b2c_clock -period 10 [get_ports chiplink_b2c_clk]
}
set group_mem [get_clocks -quiet {clk_pll_i}]
set group_sys [get_clocks -quiet {sys_diff_clk \
clk_out*_vc707_sys_clock_mmcm1 \
clk_out*_vc707_sys_clock_mmcm2}]
set group_cl [get_clocks -quiet {chiplink_b2c_clock \
clk_out*_vc707_sys_clock_mmcm3}]
set group_pci [get_clocks -quiet -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]]
puts "group_mem: $group_mem"
puts "group_sys: $group_sys"
puts "group_pci: $group_pci"
puts "group_cl: $group_cl"
set groups [list]
if { [llength $group_mem] > 0 } { lappend groups -group $group_mem }
if { [llength $group_sys] > 0 } { lappend groups -group $group_sys }
if { [llength $group_pci] > 0 } { lappend groups -group $group_pci }
if { [llength $group_cl] > 0 } { lappend groups -group $group_cl }
puts "set_clock_groups -asynchronous $groups"
set_clock_groups -asynchronous {*}$groups

21
xilinx/vc707/constraints/vc707-master.xdc
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@ -71,24 +71,3 @@ set_property -dict { PACKAGE_PIN AR30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRU
set_property -dict { PACKAGE_PIN AU31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[1]}] set_property -dict { PACKAGE_PIN AU31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[1]}]
set_property -dict { PACKAGE_PIN AV31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[2]}] set_property -dict { PACKAGE_PIN AV31 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[2]}]
set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[3]}] set_property -dict { PACKAGE_PIN AT30 IOSTANDARD LVCMOS18 IOB TRUE PULLUP TRUE } [get_ports {sdio_dat[3]}]
create_clock -name chiplink_b2c_clock -period 10 [get_ports chiplink_b2c_clk]
set_clock_groups -asynchronous \
-group { clk_pll_i } \
-group { \
sys_diff_clk \
clk_out1_vc707_sys_clock_mmcm2 \
clk_out2_vc707_sys_clock_mmcm2 \
clk_out3_vc707_sys_clock_mmcm2 \
clk_out4_vc707_sys_clock_mmcm2 \
clk_out5_vc707_sys_clock_mmcm2 \
clk_out6_vc707_sys_clock_mmcm2 \
clk_out7_vc707_sys_clock_mmcm2 } \
-group { \
clk_out1_vc707_sys_clock_mmcm1 \
clk_out2_vc707_sys_clock_mmcm1 } \
-group { \
clk_out1_vc707_sys_clock_mmcm3 \
chiplink_b2c_clock } \
-group [list [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name =~ *pcie*TXOUTCLK}]]]