riscv/fpga-shells
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Remove unused UART signals (rs and cs) from ml507

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This commit is contained in:
Klemens Schölhorn 2018-04-18 00:26:00 +02:00
parent e9625bf8ee
commit 41362a1cb5
1 changed files with 0 additions and 4 deletions
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4
src/main/scala/shell/xilinx/ML507Shell.scala
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@ -105,8 +105,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
// UART // UART
val uart_tx = IO(Output(Bool())) val uart_tx = IO(Output(Bool()))
val uart_rx = IO(Input(Bool())) val uart_rx = IO(Input(Bool()))
val uart_rtsn = IO(Output(Bool()))
val uart_ctsn = IO(Input(Bool()))
// SDIO // SDIO
val sdio_clk = IO(Output(Bool())) val sdio_clk = IO(Output(Bool()))
@ -225,8 +223,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
// UART // UART
//----------------------------------------------------------------------- //-----------------------------------------------------------------------
uart_rtsn := false.B
def connectUART(dut: HasPeripheryUARTModuleImp): Unit = { def connectUART(dut: HasPeripheryUARTModuleImp): Unit = {
val uartParams = p(PeripheryUARTKey) val uartParams = p(PeripheryUARTKey)
if (!uartParams.isEmpty) { if (!uartParams.isEmpty) {