From 41362a1cb54cb28be1b2a960bbdc59403b480611 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Klemens=20Sch=C3=B6lhorn?= <klemens@schoelhorn.eu>
Date: Wed, 18 Apr 2018 00:26:00 +0200
Subject: [PATCH] Remove unused UART signals (rs and cs) from ml507

---
 src/main/scala/shell/xilinx/ML507Shell.scala | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/src/main/scala/shell/xilinx/ML507Shell.scala b/src/main/scala/shell/xilinx/ML507Shell.scala
index 158c422..27e0035 100644
--- a/src/main/scala/shell/xilinx/ML507Shell.scala
+++ b/src/main/scala/shell/xilinx/ML507Shell.scala
@@ -105,8 +105,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
   // UART
   val uart_tx              = IO(Output(Bool()))
   val uart_rx              = IO(Input(Bool()))
-  val uart_rtsn            = IO(Output(Bool()))
-  val uart_ctsn            = IO(Input(Bool()))
 
   // SDIO
   val sdio_clk             = IO(Output(Bool()))
@@ -225,8 +223,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
   // UART
   //-----------------------------------------------------------------------
 
-  uart_rtsn := false.B
-
   def connectUART(dut: HasPeripheryUARTModuleImp): Unit = {
     val uartParams = p(PeripheryUARTKey)
     if (!uartParams.isEmpty) {