computer/firmware/alu
2020-02-24 22:15:34 +01:00
..
tests Ad test bench for the computer control logic 2018-05-31 22:31:15 +02:00
.gitignore Add top modules and pin constraints for the two ALU CPLDs 2018-07-26 21:44:35 +02:00
adder.vhd Add toy alu with initial testbench 2018-03-09 01:52:19 +01:00
alu.vhd Add top modules and pin constraints for the two ALU CPLDs 2018-07-26 21:44:35 +02:00
alu.xise Create 6 bit version for two XC9536XL CPLDs 2020-02-24 22:15:34 +01:00
CPLD1.ucf Create 6 bit version for two XC9536XL CPLDs 2020-02-24 22:15:34 +01:00
CPLD1.vhd Create 6 bit version for two XC9536XL CPLDs 2020-02-24 22:15:34 +01:00
CPLD2.ucf Create 6 bit version for two XC9536XL CPLDs 2020-02-24 22:15:34 +01:00
CPLD2.vhd Create 6 bit version for two XC9536XL CPLDs 2020-02-24 22:15:34 +01:00