Ad test bench for the computer control logic
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611e0ac388
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@ -24,9 +24,13 @@
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="tests/toy_16.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="36"/>
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</file>
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<file xil_pn:name="tests/control_logic.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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</file>
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</files>
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<properties>
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@ -82,9 +86,9 @@
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<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
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<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|main|rtl" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="main.vhd" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|control_logic|test" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="tests/control_logic.vhd" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/control_logic" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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@ -136,10 +140,10 @@
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<property xil_pn:name="Package" xil_pn:value="PC44" xil_pn:valueState="default"/>
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<property xil_pn:name="Pin Feedback" xil_pn:value="On" xil_pn:valueState="default"/>
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<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="main_map.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="main_timesim.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="main_synthesis.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="main_translate.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="control_logic_map.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="control_logic_timesim.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="control_logic_synthesis.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="control_logic_translate.v" xil_pn:valueState="default"/>
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<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
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@ -158,8 +162,8 @@
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<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/toy_16" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.toy_16" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/control_logic" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.control_logic" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
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@ -173,7 +177,7 @@
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<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.toy_16" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.control_logic" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-7" xil_pn:valueState="default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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@ -213,7 +217,7 @@
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<!-- -->
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<!-- The following properties are for internal use only. These should not be modified.-->
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<!-- -->
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|toy_16|test" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|control_logic|test" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DesignName" xil_pn:value="alu" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
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@ -0,0 +1,149 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity control_logic is
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end control_logic;
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architecture test of control_logic is
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component main
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generic (
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FIRST: boolean
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);
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port (
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func: in std_logic_vector(3 downto 0);
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accu: in std_logic_vector(7 downto 0);
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ram: in std_logic_vector(7 downto 0);
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carry_in: in std_logic;
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result: out std_logic_vector(7 downto 0);
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carry_out: out std_logic
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);
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end component;
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type ram_type is array(0 to 4095) of std_logic_vector(15 downto 0);
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signal clk: std_logic;
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signal first: boolean := false;
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signal acc: std_logic_vector(15 downto 0) := (others => '0');
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signal ir: std_logic_vector(15 downto 0) := (others => '0');
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signal ram: ram_type := (
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0 => "0001000000001010",
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1 => "0011000000001000",
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2 => "0000000000001010",
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3 => "1011000000000000",
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4 => "0010000000000000",
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5 => "0000000000000000",
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6 => "0000000000000101",
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7 => "0000000000000111",
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8 => "0001001110001000",
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9 => "0000000000000000",
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10 => "0000000000000000",
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others => (others => '0')
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);
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signal pc: std_logic_vector(11 downto 0) := (others => '0');
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signal data_out: std_logic_vector(15 downto 0);
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signal data_in: std_logic_vector(15 downto 0);
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signal carry_propagation: std_logic;
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signal addr: std_logic_vector(11 downto 0);
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signal op: std_logic_vector(3 downto 0);
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signal write_ram: std_logic;
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signal write_pc: std_logic;
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signal inc_pc: std_logic;
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signal ram_addr_ir: std_logic;
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signal write_ir: std_logic;
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signal write_acc: std_logic;
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begin
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op <= ir(15 downto 12);
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addr <= ir(11 downto 0) when ram_addr_ir = '1' else pc;
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data_out <= ram(to_integer(unsigned(addr)));
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alu1: main generic map (
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FIRST => true
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) port map (
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func => op,
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accu => acc(7 downto 0),
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ram => data_out(7 downto 0),
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carry_in => '0',
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result => data_in(7 downto 0),
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carry_out => carry_propagation
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);
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alu2: main generic map (
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FIRST => false
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) port map (
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func => op,
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accu => acc(15 downto 8),
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ram => data_out(15 downto 8),
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carry_in => carry_propagation,
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result => data_in(15 downto 8),
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carry_out => open
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);
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process(clk)
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begin
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if rising_edge(clk) then
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if write_acc = '1' then
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acc <= data_in;
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end if;
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if write_ir = '1' then
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ir <= data_out;
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end if;
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if write_ram = '1' then
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ram(to_integer(unsigned(addr))) <= data_in;
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end if;
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if write_pc = '1' then
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pc <= ir(11 downto 0);
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elsif inc_pc = '1' then
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pc <= std_logic_vector(unsigned(pc) + 1);
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end if;
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end if;
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end process;
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process(first, op, acc)
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begin
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write_ram <= '0';
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write_pc <= '0';
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inc_pc <= '0';
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ram_addr_ir <= '1';
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write_ir <= '0';
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write_acc <= '1';
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if first then
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if op = "0000" then
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write_ram <= '1';
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end if;
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if acc = "0000000000000000" and op = "0010" then
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write_pc <= '1';
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end if;
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if op = "0000" or op = "0010" or op(3 downto 2) = "11" then
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write_acc <= '0';
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end if;
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else
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inc_pc <= '1';
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ram_addr_ir <= '0';
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write_ir <= '1';
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write_acc <= '0';
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end if;
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end process;
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process(clk)
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begin
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if rising_edge(clk) then
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first <= not first;
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end if;
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end process;
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process
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begin
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clk <= '1';
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wait for 1us;
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clk <= '0';
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wait for 1us;
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end process;
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end test;
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