Add toy alu with initial testbench
This commit is contained in:
parent
116d97f508
commit
091884bab2
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# intermediate build files
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*.bgn
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*.bit
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*.bld
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*.cmd_log
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*.drc
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*.ll
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*.lso
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*.msd
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*.msk
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*.ncd
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*.ngc
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*.ngd
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*.ngr
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*.pad
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*.par
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*.pcf
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*.prj
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*.ptwx
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*.rbb
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*.rbd
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*.stx
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*.syr
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*.twr
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*.twx
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*.unroutes
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*.ut
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*.xpi
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*.xst
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*_bitgen.xwbt
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*_envsettings.html
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*_map.map
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*_map.mrp
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*_map.ngm
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*_map.xrpt
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*_ngdbuild.xrpt
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*_pad.csv
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*_pad.txt
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*_par.xrpt
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*_summary.html
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*_summary.xml
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*_usage.xml
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*_xst.xrpt
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# iMPACT generated files
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_impactbatch.log
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impact.xsl
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impact_impact.xwbt
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ise_impact.cmd
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webtalk_impact.xml
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# Core Generator generated files
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xaw2verilog.log
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# project-wide generated files
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*.gise
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par_usage_statistics.html
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usage_statistics_webtalk.html
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webtalk.log
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webtalk_pn.xml
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# generated folders
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iseconfig/
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xlnx_auto_0_xdb/
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xst/
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_ngo/
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_xmsgs/
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# isim
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/isim*
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/fuse*
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*.exe
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*.wdb
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xilinxsim.ini
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# log files
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*.log
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# ip cores
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/ipcore_dir/*.cgc
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/ipcore_dir/*.cgp
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/ipcore_dir/*.tcl
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/ipcore_dir/*.vhd
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/ipcore_dir/*flist.txt
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/ipcore_dir/_xmsgs/
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/ipcore_dir/tmp/
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# cpld
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/main_html/
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*.gyd
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*.jed
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*.mfd
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*.nga
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*.pnx
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*.rpt
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*.vm6
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*.xml
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*.err
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@ -0,0 +1,30 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.ALL;
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entity adder is
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generic (
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WIDTH: integer
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);
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port (
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x: in std_logic_vector(WIDTH-1 downto 0);
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y: in std_logic_vector(WIDTH-1 downto 0);
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cin: in std_logic;
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sum: out std_logic_vector(WIDTH-1 downto 0);
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cout: out std_logic
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);
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end adder;
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architecture rtl of adder is
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signal result: unsigned(WIDTH downto 0);
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begin
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result <= resize(unsigned(x), WIDTH+1) +
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resize(unsigned(y), WIDTH+1) +
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("" & cin);
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sum <= std_logic_vector(result(WIDTH-1 downto 0));
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cout <= result(WIDTH);
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end rtl;
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@ -0,0 +1,245 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<header>
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<!-- ISE source project file created by Project Navigator. -->
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<!-- -->
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<!-- This file contains project source information including a list of -->
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<!-- project source files, project and process properties. This file, -->
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<!-- along with the project source files, is sufficient to open and -->
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<!-- implement in ISE Project Navigator. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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</header>
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<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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<files>
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<file xil_pn:name="main.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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<file xil_pn:name="adder.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="tests/toy_16.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="36"/>
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</file>
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</files>
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<properties>
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<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
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<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
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<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
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<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
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<property xil_pn:name="Collapsing Input Limit (2-36)" xil_pn:value="36" xil_pn:valueState="default"/>
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<property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
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<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
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<property xil_pn:name="Device" xil_pn:value="xc9572" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Device Family" xil_pn:value="XC9500 CPLDs" xil_pn:valueState="non-default"/>
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||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-7" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Enable FASTConnect/UIM optimization" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|main|rtl" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="main.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Local Macrocell Feedback" xil_pn:value="On" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="PC44" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pin Feedback" xil_pn:value="On" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="main_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="main_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="main_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="main_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/toy_16" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.toy_16" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Signature /User Code" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.toy_16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-7" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCIO Reference Voltage" xil_pn:value="LVTTL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|toy_16|test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="alu" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2018-02-08T21:54:09" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8B4B617B25B013D12B323E2BBA3E1D9B" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
library ieee;
|
||||
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.ALL;
|
||||
|
||||
entity main is
|
||||
generic (
|
||||
WIDTH: integer := 8
|
||||
);
|
||||
port (
|
||||
func: in std_logic_vector(3 downto 0);
|
||||
accu: in std_logic_vector(WIDTH-1 downto 0);
|
||||
ram: in std_logic_vector(WIDTH-1 downto 0);
|
||||
carry_in: in std_logic;
|
||||
result: out std_logic_vector(WIDTH-1 downto 0);
|
||||
carry_out: out std_logic
|
||||
);
|
||||
end main;
|
||||
|
||||
architecture rtl of main is
|
||||
signal x: std_logic_vector(WIDTH-1 downto 0);
|
||||
signal y: std_logic_vector(WIDTH-1 downto 0);
|
||||
signal cin: std_logic;
|
||||
signal sum: std_logic_vector(WIDTH-1 downto 0);
|
||||
signal cout: std_logic;
|
||||
begin
|
||||
|
||||
adder: entity work.adder generic map (
|
||||
WIDTH => WIDTH
|
||||
) port map (
|
||||
x => x,
|
||||
y => y,
|
||||
cin => cin,
|
||||
sum => sum,
|
||||
cout => cout
|
||||
);
|
||||
|
||||
process(func, accu, ram, carry_in, sum, cout)
|
||||
variable carry: std_logic;
|
||||
begin
|
||||
-- This default value will be overwritten in the add/sub cases
|
||||
carry_out <= '0';
|
||||
|
||||
-- Avoid generating latches by leaving the adder inputs unspecified
|
||||
-- when it is not beeing used (otherwise these are overwritten)
|
||||
x <= (others => '-');
|
||||
y <= (others => '-');
|
||||
cin <= '-';
|
||||
|
||||
case func is
|
||||
when "0000" => -- STORE
|
||||
result <= accu;
|
||||
when "0001" => -- LOAD
|
||||
result <= ram;
|
||||
when "0010" => -- JMP
|
||||
result <= (others => '-');
|
||||
when "0011" => -- ADD
|
||||
x <= accu;
|
||||
y <= ram;
|
||||
cin <= carry_in;
|
||||
result <= sum;
|
||||
carry_out <= cout;
|
||||
when "0100" => -- SUB
|
||||
x <= accu;
|
||||
y <= not ram;
|
||||
cin <= not carry_in;
|
||||
result <= sum;
|
||||
carry_out <= not cout;
|
||||
when "0101" => -- OR
|
||||
result <= accu or ram;
|
||||
when "0110" => -- AND
|
||||
result <= accu and ram;
|
||||
when "0111" => -- XOR
|
||||
result <= accu xor ram;
|
||||
when "1000" => -- NOT
|
||||
result <= not accu;
|
||||
when "1001" => -- INC
|
||||
x <= accu;
|
||||
y <= (others => '0');
|
||||
cin <= '1';
|
||||
result <= sum;
|
||||
carry_out <= cout;
|
||||
when "1010" => -- DEC
|
||||
x <= accu;
|
||||
y <= (others => '1');
|
||||
cin <= '0';
|
||||
result <= sum;
|
||||
carry_out <= not cout;
|
||||
when "1011" => -- ZERO
|
||||
result <= (others => '0');
|
||||
when others => -- NOPs
|
||||
result <= (others => '-');
|
||||
end case;
|
||||
end process;
|
||||
|
||||
end rtl;
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
library ieee;
|
||||
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity toy_16 is
|
||||
end toy_16;
|
||||
|
||||
architecture test of toy_16 is
|
||||
|
||||
constant period: time := 1us;
|
||||
|
||||
component main
|
||||
port (
|
||||
func: in std_logic_vector(3 downto 0);
|
||||
accu: in std_logic_vector(7 downto 0);
|
||||
ram: in std_logic_vector(7 downto 0);
|
||||
carry_in: in std_logic;
|
||||
result: out std_logic_vector(7 downto 0);
|
||||
carry_out: out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
--Inputs
|
||||
signal func: std_logic_vector(3 downto 0) := (others => '0');
|
||||
signal accu: std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal ram: std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal carry_in: std_logic := '0';
|
||||
|
||||
--Outputs
|
||||
signal result: std_logic_vector(15 downto 0);
|
||||
signal carry_out: std_logic;
|
||||
|
||||
-- Internal signals
|
||||
signal carry_propagation: std_logic;
|
||||
|
||||
-- Test constants
|
||||
constant A: std_logic_vector(15 downto 0) := "1010101010101010";
|
||||
constant B: std_logic_vector(15 downto 0) := "1100110011001100";
|
||||
|
||||
-- Info String (driven by procedure in test_process)
|
||||
signal info_string: string(1 to 10);
|
||||
|
||||
begin
|
||||
|
||||
alu1: main port map (
|
||||
func => func,
|
||||
accu => accu(7 downto 0),
|
||||
ram => ram(7 downto 0),
|
||||
carry_in => '0',
|
||||
result => result(7 downto 0),
|
||||
carry_out => carry_propagation
|
||||
);
|
||||
|
||||
alu2: main port map (
|
||||
func => func,
|
||||
accu => accu(15 downto 8),
|
||||
ram => ram(15 downto 8),
|
||||
carry_in => carry_propagation,
|
||||
result => result(15 downto 8),
|
||||
carry_out => open
|
||||
);
|
||||
|
||||
test_process: process
|
||||
procedure info(info: string) is
|
||||
begin
|
||||
info_string <= (others => ' ');
|
||||
info_string(1 to info'length) <= info;
|
||||
end procedure;
|
||||
begin
|
||||
--
|
||||
-- logic tests
|
||||
--
|
||||
accu <= A; ram <= B; carry_in <= '0';
|
||||
|
||||
info("STORE");
|
||||
func <= "0000";
|
||||
wait for period;
|
||||
assert result = A report "STORE failed";
|
||||
|
||||
info("LOAD");
|
||||
func <= "0001";
|
||||
wait for period;
|
||||
assert result = B report "LOAD failed";
|
||||
|
||||
info("OR");
|
||||
func <= "0101";
|
||||
wait for period;
|
||||
assert result = (A or B) report "OR failed";
|
||||
|
||||
info("AND");
|
||||
func <= "0110";
|
||||
wait for period;
|
||||
assert result = (A and B) report "AND failed";
|
||||
|
||||
info("XOR");
|
||||
func <= "0111";
|
||||
wait for period;
|
||||
assert result = (A xor B) report "XOR failed";
|
||||
|
||||
info("NOT");
|
||||
func <= "1000";
|
||||
wait for period;
|
||||
assert result = not A report "NOT failed";
|
||||
|
||||
info("ZERO");
|
||||
func <= "1011";
|
||||
wait for period;
|
||||
assert result = "0000000000000000" report "ZERO failed";
|
||||
|
||||
--
|
||||
-- arithmatic tests
|
||||
--
|
||||
|
||||
info("ADD");
|
||||
accu <= "0100010011110011";
|
||||
ram <= "0011100010101010"; carry_in <= '0';
|
||||
func <= "0011";
|
||||
wait for period;
|
||||
assert result = "0111110110011101" report "ADD failed";
|
||||
|
||||
info("SUB");
|
||||
accu <= "0100010000110011";
|
||||
ram <= "0011100000101010"; carry_in <= '0';
|
||||
func <= "0100";
|
||||
wait for period;
|
||||
assert result = "0000110000001001" report "SUB failed";
|
||||
|
||||
info("SUB-B");
|
||||
accu <= "0100010010110011";
|
||||
ram <= "0011100011101010"; carry_in <= '0';
|
||||
func <= "0100";
|
||||
wait for period;
|
||||
assert result = "0000101111001001" report "SUB failed";
|
||||
|
||||
-- terminate test
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
end test;
|
||||
Loading…
Reference in New Issue