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Klemens Schölhorn
34f837d7b1 Add build instructions and license 2018-06-05 18:03:24 +02:00
Klemens Schölhorn
ce76d77699 Add missing module to the ISE project and ignore generated MIG-Core 2018-06-05 17:15:48 +02:00
Klemens Schölhorn
dfd2d2ac9b Use new ise virtex-6 parser and set SYNTHESIS verilog constant 2018-06-05 16:10:42 +02:00
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parts of the General Public License. Of course, your program's commands
might be different; for a GUI interface, you would use an "about box".
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU GPL, see
<https://www.gnu.org/licenses/>.
The GNU General Public License does not permit incorporating your program
into proprietary programs. If your program is a subroutine library, you
may consider it more useful to permit linking proprietary applications with
the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
<https://www.gnu.org/licenses/why-not-lgpl.html>.

161
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@ -0,0 +1,161 @@
# RISC-V Linux-Workstation auf dem ML507
Dieses Repository enthält die Implementierung einer RISC-V-Workstation
für das Xilinx ML507-Entwicklungsboard mit Unterstützung für das Booten
von Linux von einer SD-Karte. Die Workstation wurde im Rahmen einer
[Masterarbeit] an der Universität Leipzig entwickelt.
## Kompilieren der RISC-V-Toolchain und des Linux-Bootimage
Da für die Synthese der Workstation aufgrund der Kompilierung des enthaltenen
Bootloaders ebenfalls eine RISC-V-Toolchain nötig ist, wird diese zuerst
zusammen mit dem Linux-Bootimage erzeugt.
```sh
cd freedom-u-sdk
make
```
Falls dabei bei einem „Bleeding edge“-System wie Arch-Linux Fehler auftreten,
können nach Bedarf die im `patches`-Ordner verfügbaren Patches angewendet
werden. Weitere Details zum Freedom-SDK finden sich u.a. im
[Freedom U500 VC707 FPGA Dev Kit Getting Started Guide].
Während des Kompilierens wird im Ordner `freedom-u-sdk/toolchain` eine RISC-V
GCC-Toolchain erstellt. Der Unterordner `bin` sollte für die folgenden
Schritte zur `PATH`-Umgebungsvariablen hinzugefügt werden.
## Synthese der Workstation für das ML507-Entwicklungsboard
### Erzeugen des Rocket-SOC
Zuerst wird der Rocket-SoC ohne das BootROM erzeugt:
```sh
cd freedom
make -f Makefile.u500ml507devkit verilog
```
Anschließend muss der dabei generierte DeviceTree
`sifive.freedom.unleashed.u500ml507devkit.U500ML507DevKitConfig.dts`
im Ordner `builds/u500ml507devkit` wie folgt angepasst werden:
1. Der verwendete Systemtakt muss zuerst im `soc`-Abschnitt definiert werden:
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <60000000>;
};
2. Anschließend wird er über `clocks = <&sysclk 0>;` in den `serial` und `spi`
Abschnitten referenziert.
3. Es muss ein Alias für den UART-Controller im Hauptlevel hinzugefügt werden:
aliases {
serial0 = &L8;
};
4. Die `dts`-Datei muss mit Hilfe des `dtc`-Programms kompiliert werden. Mit
dem Ergebniss sollte die in `builds/u500ml507devkit` vorhandenen `dtb`-
Datei überschrieben werden.
Um diese Schritte zu vereinfachen, enthält der `patches`-Ordner bereits
fertig angepasste `dts` und `dtb`-Dateien, mit denen die vorhandenen
ersetzt werden können.
Schließlich wird das noch fehlende BootROM erzeugt, wobei dabei auch
der Bootloader kompiliert wird:
```sh
make -f Makefile.u500ml507devkit romgen
```
### Erzeugen des MIG-Speichercontrollers
Da der von MIG erzeugte Speichercontroller nicht ohne weiteres weitergegeben
werden darf, muss er von Hand dem ISE-Projekt hinzugefügt werden. Falls beim
öffnen des ISE-Projektes eine Meldung bezüglich fehlender Dateien erscheint,
wurde entweder der Rocket-SoC nicht korrekt erzeugt oder nicht alle git-
Submodule korrekt geklont.
1. Rechtsklick auf das Projekt, *New Source…*
2. *IP (Core Generator & Architecture Wizard)* auswählen
3. Als Dateinamen `ddr2_controller` angeben, *Location* übernehmen
4. MIG auswählen (zB über die Suche), *Next*, *Finish* -> MIG startet
5. Prüfen, ob der korrekte FPGA ausgewählt ist
6. Bei den Ausgabeoptionen nochmals den Namen überprüfen und *Create Design*
auswählen
7. Es sollten keine PIN-kompatiblen FPGAs oder der PPC440 ausgewählt werden
8. `DDR2 SDRAM` als Speichertyp auswählen
9. 5000 ps / 200 MHz als Takt, bei *Memory Type* `SODIMMs`, bei *Memory Part*
das gewünschte Speichermodul (zB `MT4HTF3264HY-667` auf dem ML507) und bei
*Date Width* `64` auswählen; Prüfen, ob *Data Mask* aktiviert ist
10. Prüfen, ob als *Burst Length* `4` ausgewählt ist
11. Den Haken bei *Use PLL* deaktivieren
12. Auf der nächsten Seite muss nichts verändert werden
13. Bei der Pin-Auswahl *New Design* auswählen und zwei mal bestätigen
14. Die Zusammenfassung sollte wie unten lauten
15. Das Memory-Modell über *Decline* nicht erzeugen lassen
16. Die PCB-Informationen bestätigen und den Controller generieren
Anschließend kann die Workstation mit einem Doppelklick auf "Generate
Programming File" synthetisiert werden. Der erzeugte FPGA-Bitstream befindet
sich im Ordner `project/ise/work` und kann per Impact auf das FPGA geladen
werden. Details zum Anschluss der SD-Karte befinden sich im Unterordner
`sd-breakout`.
```text
CORE Generator Options:
Target Device : xc5vfx70t-ff1136
Speed Grade : -1
HDL : verilog
Synthesis Tool : ISE
MIG Output Options:
Module Name : ddr2_controller
No of Controllers : 1
Selected Compatible Device(s) : --
PPC440 : --
PowerPC440 Block Selection : --
FPGA Options:
PLL : disabled
Debug Signals : Disable
System Clock : Single-Ended
Limit to 2 Bytes per Bank : disabled
Extended FPGA Options:
DCI for DQ/DQS : enabled
DCI for Address/Control : disabled
Class for Address and Control : Class II
Controller Options:
Memory : DDR2_SDRAM
Design Clock Frequency : 5000 ps(200.00 MHz)
Memory Type : SODIMMs
Memory Part : MT4HTF3264HY-667
Equivalent Part(s) : --
Data Width : 64
Memory Depth : 1
ECC : ECC Disabled
Data Mask : enabled
Memory Options:
Burst Length (MR[2:0]) : 4(010)
Burst Type (MR[3]) : sequential(0)
CAS Latency (MR[6:4]) : 4(100)
Output Drive Strength (EMR[1]) : Fullstrength(0)
RTT (nominal) - ODT (EMR[6,2]) : 75ohms(01)
Additive Latency (EMR[5:3]) : 0(000)
FPGA Options:
IODELAY Performance Mode : HIGH
```
## Lizenzen
Alle Komponenten der Workstation sind, wenn nicht anders gekennzeichnet,
unter GPLv3 lizenziert. Der für den FPGA erzeugte Bitstream darf jedoch
nicht unter GPLv3 und damit gar nicht weitergegeben werden, da er den
MIG-Speichercontroller enthält, dessen Quellcode nur unter ganz bestimmten
Bedingungen modifiziert und weitergegeben werden darf.
Die Freedom-Platform ist unter der GPLv3-kompatiblen Apache2 Lizenz und
Rocket außerdem unter der BSD-Lizenz lizenziert. Linux ist ausschließlich
unter GPLv2 lizenziert.
[Masterarbeit]: https://klemens.schoelhorn.eu/abschlussarbeiten/
[Freedom U500 VC707 FPGA Dev Kit Getting Started Guide]: https://static.dev.sifive.com/SiFive-U500-vc707-gettingstarted-v0.2.pdf

30
patches/buildroot-automake.patch Normal file
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@ -0,0 +1,30 @@
From 13f00eb4493c217269b76614759e452d8302955e Mon Sep 17 00:00:00 2001
From: Paul Eggert <eggert@cs.ucla.edu>
Date: Thu, 31 Mar 2016 16:35:29 -0700
Subject: automake: port to Perl 5.22 and later
Without this change, Perl 5.22 complains "Unescaped left brace in
regex is deprecated" and this is planned to become a hard error in
Perl 5.26. See:
http://search.cpan.org/dist/perl-5.22.0/pod/perldelta.pod#A_literal_%22{%22_should_now_be_escaped_in_a_pattern
* bin/automake.in (substitute_ac_subst_variables): Escape left brace.
---
bin/automake.in | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bin/automake.in b/bin/automake.in
index a3a0aa3..2c8f31e 100644
--- a/bin/automake.in
+++ b/bin/automake.in
@@ -3878,7 +3878,7 @@ sub substitute_ac_subst_variables_worker
sub substitute_ac_subst_variables
{
my ($text) = @_;
- $text =~ s/\${([^ \t=:+{}]+)}/substitute_ac_subst_variables_worker ($1)/ge;
+ $text =~ s/\$[{]([^ \t=:+{}]+)}/substitute_ac_subst_variables_worker ($1)/ge;
return $text;
}
--
cgit v1.0-41-gc330

90
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@ -0,0 +1,90 @@
Date: Fri, 29 Dec 2017 10:19:51 -0800
From: Palmer Dabbelt <palmer@...belt.com>
To: linux-ext4@...r.kernel.org, tytso@....edu
Cc: patches@...ups.riscv.org, Palmer Dabbelt <palmer@...belt.com>
Subject: [PATCH v2] Rename copy_file_range to copy_file_chunk
As of 2.27, glibc will have a copy_file_range library call to wrap the
new copy_file_range system call. This conflicts with the function in
misc/create_inode.c, which this patch renames _copy_file_range.
Full disclosure: I found this when building e2fsprogs for RISC-V with a
glibc-2.27 prerelease, so it's very possible I screwed something up
here. Here's the relevant glibc commit:
commit bad7a0c81f501fbbcc79af9eaa4b8254441c4a1f
Author: Florian Weimer <fweimer@...hat.com>
Date: Fri Dec 22 10:55:40 2017 +0100
copy_file_range: New function to copy file data
The semantics are based on the Linux system call, but a very close
emulation in user space is provided.
...
diff --git a/posix/unistd.h b/posix/unistd.h
index 32b0f4898fd2..65317c79fd39 100644
--- a/posix/unistd.h
+++ b/posix/unistd.h
@@ -1105,7 +1105,12 @@ extern int lockf64 (int __fd, int __cmd, __off64_t __len) __wur;
do __result = (long int) (expression); \
while (__result == -1L && errno == EINTR); \
__result; }))
-#endif
+
+/* Copy LENGTH bytes from INFD to OUTFD. */
+ssize_t copy_file_range (int __infd, __off64_t *__pinoff,
+ int __outfd, __off64_t *__poutoff,
+ size_t __length, unsigned int __flags);
+#endif /* __USE_GNU */
Changes since v1:
* The new name is now copy_file_chunk instead of _copy_file_range.
Signed-off-by: Palmer Dabbelt <palmer@...belt.com>
---
misc/create_inode.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/misc/create_inode.c b/misc/create_inode.c
index a07f8328e5f9..51d25f8fb005 100644
--- a/misc/create_inode.c
+++ b/misc/create_inode.c
@@ -398,7 +398,7 @@ static ssize_t my_pread(int fd, void *buf, size_t count, off_t offset)
}
#endif /* !defined HAVE_PREAD64 && !defined HAVE_PREAD */
-static errcode_t copy_file_range(ext2_filsys fs, int fd, ext2_file_t e2_file,
+static errcode_t copy_file_chunk(ext2_filsys fs, int fd, ext2_file_t e2_file,
off_t start, off_t end, char *buf,
char *zerobuf)
{
@@ -472,7 +472,7 @@ static errcode_t try_lseek_copy(ext2_filsys fs, int fd, struct stat *statbuf,
data_blk = data & ~(fs->blocksize - 1);
hole_blk = (hole + (fs->blocksize - 1)) & ~(fs->blocksize - 1);
- err = copy_file_range(fs, fd, e2_file, data_blk, hole_blk, buf,
+ err = copy_file_chunk(fs, fd, e2_file, data_blk, hole_blk, buf,
zerobuf);
if (err)
return err;
@@ -523,7 +523,7 @@ static errcode_t try_fiemap_copy(ext2_filsys fs, int fd, ext2_file_t e2_file,
goto out;
for (i = 0, ext = ext_buf; i < fiemap_buf->fm_mapped_extents;
i++, ext++) {
- err = copy_file_range(fs, fd, e2_file, ext->fe_logical,
+ err = copy_file_chunk(fs, fd, e2_file, ext->fe_logical,
ext->fe_logical + ext->fe_length,
buf, zerobuf);
if (err)
@@ -576,7 +576,7 @@ static errcode_t copy_file(ext2_filsys fs, int fd, struct stat *statbuf,
goto out;
#endif
- err = copy_file_range(fs, fd, e2_file, 0, statbuf->st_size, buf,
+ err = copy_file_chunk(fs, fd, e2_file, 0, statbuf->st_size, buf,
zerobuf);
out:
ext2fs_free_mem(&zerobuf);
--
2.13.6

31
patches/buildroot-libtirpc.patch Normal file
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@ -0,0 +1,31 @@
From 1521836c4e0d173767d7417fcc2682cb19ca8aba Mon Sep 17 00:00:00 2001
From: Dagg Stompler <daggs@gmx.com>
Date: Fri, 29 Dec 2017 15:03:33 +0200
Subject: [PATCH] libtirpc: fix compilation error of rpcgen
When compiling libtirpc, without RPC support available on the host
machine, the build of the rpcgen host program because it cannot find
the netconfig.h and rpc/types.h headers. Instead of relying on the
system-provided ones, let's use the ones included in the libtirpc
source code by patching the rpcgen build logic.
Signed-off-by: Dagg Stompler <daggs@gmx.com>
[Thomas: reword commit log.]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
package/libtirpc/0003-Add-rpcgen-program-from-nfs-utils-sources.patch | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/package/libtirpc/0003-Add-rpcgen-program-from-nfs-utils-sources.patch b/package/libtirpc/0003-Add-rpcgen-program-from-nfs-utils-sources.patch
index 1cf861417c..f2b15fe2f1 100644
--- a/package/libtirpc/0003-Add-rpcgen-program-from-nfs-utils-sources.patch
+++ b/package/libtirpc/0003-Add-rpcgen-program-from-nfs-utils-sources.patch
@@ -83,7 +83,7 @@ index 0000000..2277b6f
--- /dev/null
+++ b/rpcgen/Makefile.am
@@ -0,0 +1,22 @@
-+COMPILE = $(CC_FOR_BUILD) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
++COMPILE = $(CC_FOR_BUILD) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) -I../tirpc $(AM_CPPFLAGS) \
+ $(CPPFLAGS_FOR_BUILD) $(AM_CFLAGS) $(CFLAGS_FOR_BUILD)
+LINK = $(CC_FOR_BUILD) $(AM_CFLAGS) $(CFLAGS_FOR_BUILD) $(AM_LDFLAGS) $(LDFLAGS_FOR_BUILD) -o $@
+

BIN
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Binary file not shown.

118
patches/sifive.freedom.unleashed.u500ml507devkit.U500ML507DevKitConfig.dts Normal file
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@ -0,0 +1,118 @@
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-unknown-dev";
model = "freechips,rocketchip-unknown";
aliases {
serial0 = &L8;
};
L15: cpus {
#address-cells = <1>;
#size-cells = <0>;
L5: cpu@0 {
clock-frequency = <60000000>;
compatible = "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <4096>;
d-tlb-sets = <1>;
d-tlb-size = <4>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <4096>;
i-tlb-sets = <1>;
i-tlb-size = <4>;
mmu-type = "riscv,sv39";
next-level-cache = <&L12>;
reg = <0>;
riscv,isa = "rv64imafdc";
status = "okay";
timebase-frequency = <1000000>;
tlb-split;
L3: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
L12: memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
L14: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
ranges;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <60000000>;
};
L1: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L3 3 &L3 7>;
reg = <0x2000000 0x10000>;
reg-names = "control";
};
L2: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
interrupts-extended = <&L3 65535>;
reg = <0x0 0x1000>;
reg-names = "control";
};
L7: error-device@3000 {
compatible = "sifive,error0";
reg = <0x3000 0x1000>;
reg-names = "mem";
};
L11: gpio@64002000 {
compatible = "sifive,gpio0";
interrupt-parent = <&L0>;
interrupts = <3 4 5 6 7 8 9 10>;
reg = <0x64002000 0x1000>;
reg-names = "control";
};
L0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&L3 11 &L3 9>;
reg = <0xc000000 0x4000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <10>;
};
L6: rom@10000 {
compatible = "sifive,maskrom0";
reg = <0x10000 0x2000>;
reg-names = "mem";
};
L8: serial@64000000 {
compatible = "sifive,uart0";
interrupt-parent = <&L0>;
interrupts = <1>;
reg = <0x64000000 0x1000>;
reg-names = "control";
clocks = <&sysclk 0>;
};
L10: spi@64001000 {
compatible = "sifive,spi0";
interrupt-parent = <&L0>;
interrupts = <2>;
reg = <0x64001000 0x1000>;
reg-names = "control";
clocks = <&sysclk 0>;
};
L9: serial@64003000 {
compatible = "klemens,terminal0";
reg = <0x64003000 0x1000>;
reg-names = "control";
clocks = <&sysclk 0>;
};
};
};

10
project/ise/.gitignore vendored
View File

@ -65,6 +65,7 @@ xlnx_auto_0_xdb/
xst/
_ngo/
_xmsgs/
/ipcore_dir/
# isim
/isim*
@ -75,12 +76,3 @@ xilinxsim.ini
# log files
*.log
# ip cores
/ipcore_dir/*.cgc
/ipcore_dir/*.cgp
/ipcore_dir/*.tcl
/ipcore_dir/*.vhd
/ipcore_dir/*flist.txt
/ipcore_dir/_xmsgs/
/ipcore_dir/tmp/

78
project/ise/risc-v-workstation.xise
View File

@ -17,81 +17,83 @@
<files>
<file xil_pn:name="../../freedom/builds/u500ml507devkit/sifive.freedom.unleashed.u500ml507devkit.U500ML507DevKitConfig.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../freedom/builds/u500ml507devkit/sifive.freedom.unleashed.u500ml507devkit.U500ML507DevKitConfig.rom.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../freedom/rocket-chip/vsrc/AsyncResetReg.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../freedom/fpga-shells/xilinx/vc707/vsrc/sdio.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../freedom/fpga-shells/xilinx/vc707/vsrc/vc707reset.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../freedom/fpga-shells/xilinx/common/vsrc/PowerOnResetFPGAOnly.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../src/memory_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../src/terminal/terminal.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../src/terminal/vga.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../src/terminal/framebuffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../src/terminal/init_ch7301c.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../src/terminal/ram_2port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../src/terminal/i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="ml507_ddr2_clock.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="ml507_dvi_clock.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="ml507_sys_clock.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../src/main.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../src/ddr2.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../freedom/rocket-chip/vsrc/plusarg_reader.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector virtex5" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
@ -106,7 +108,6 @@
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
@ -153,35 +154,29 @@
<property xil_pn:name="Device Family" xil_pn:value="Virtex5" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-1" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
@ -208,9 +203,7 @@
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
@ -229,10 +222,9 @@
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to System Monitor Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="non-default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
@ -249,7 +241,6 @@
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
@ -258,7 +249,6 @@
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
@ -277,7 +267,7 @@
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="-use_new_parser yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="U500ML507DevKitFPGAChip" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
@ -286,9 +276,9 @@
<property xil_pn:name="Package" xil_pn:value="ff1136" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
@ -298,25 +288,24 @@
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="U500ML507DevKitFPGAChip_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="non-default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
@ -340,7 +329,6 @@
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="SelectMAP Abort Sequence" xil_pn:value="Enable" xil_pn:valueState="default"/>
@ -349,9 +337,7 @@
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
@ -367,7 +353,6 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@ -395,23 +380,20 @@
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="SYNTHESIS" xil_pn:valueState="non-default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events) virtex5" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="work" xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>