Add i2c init procedure sketch

dvi_test.xise

@@ -17,7 +17,7 @@
   <files>
     <file xil_pn:name="vga.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="vga_test.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
@@ -27,19 +27,26 @@
     </file>
     <file xil_pn:name="i2c_master.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="main.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="ipcore_dir/clock_source.xaw" xil_pn:type="FILE_XAW">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="init_ch7301c.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
+    <file xil_pn:name="init_ch7301c.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
   </files>
 
   <properties>
@@ -159,9 +166,9 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|main|Behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|init_ch7301c|Behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="main.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="init_ch7301c.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/init_ch7301c" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -221,7 +228,7 @@
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="init_ch7301c" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -234,10 +241,10 @@
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="main_map.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="init_ch7301c_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="main_timesim.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="init_ch7301c_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="main_synthesis.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="init_ch7301c_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="main_translate.vhd" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="init_ch7301c_translate.vhd" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -260,7 +267,7 @@
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="main" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="init_ch7301c" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -371,6 +378,7 @@
 
   <bindings>
     <binding xil_pn:location="/main" xil_pn:name="main.ucf"/>
+    <binding xil_pn:location="/main" xil_pn:name="init_ch7301c.ucf"/>
   </bindings>
 
   <libraries/>

init_ch7301c.ucf

@@ -0,0 +1,15 @@
+
+NET "i2c_scl" LOC = U27;
+NET "i2c_sda" LOC = T29;
+
+NET "led(0)" LOC = H18;
+NET "led(1)" LOC = L18;
+NET "led(2)" LOC = G15;
+NET "led(3)" LOC = AD26;
+NET "led(4)" LOC = G16;
+NET "led(5)" LOC = AD25;
+NET "led(6)" LOC = AD24;
+NET "led(7)" LOC = AE24;
+
+NET "clk" LOC = AG18;
+NET "clk" PERIOD = 27 MHz HIGH 50%;

init_ch7301c.vhd

@@ -0,0 +1,82 @@
+library ieee;
+library unisim;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+-- Xilinx primitives (???)
+use unisim.VComponents.all;
+
+entity init_ch7301c is
+    port (
+        clk: in std_logic;
+
+        i2c_scl: inout std_logic;
+        i2c_sda: inout std_logic;
+
+        led: out std_logic_vector(7 downto 0)
+    );
+end init_ch7301c;
+
+architecture Behavioral of init_ch7301c is
+    signal i2c_execute: std_logic := '0';
+    signal i2c_busy: std_logic;
+    signal i2c_busy_old: std_logic;
+    signal i2c_address: std_logic_vector(6 downto 0);
+    signal i2c_write: std_logic;
+    signal i2c_data_in: std_logic_vector(7 downto 0);
+    signal i2c_data_out: std_logic_vector(7 downto 0);
+begin
+
+    i2c_master: entity work.i2c_master generic map (
+        input_clk => 27_000_000,
+        bus_clk => 100_000
+    ) port map (
+        clk => clk,
+        reset_n => '1',
+        ena => i2c_execute,
+        addr => i2c_address,
+        rw => not i2c_write,
+        data_wr => i2c_data_in,
+        busy => i2c_busy,
+        data_rd => i2c_data_out,
+        ack_error => open,
+        sda => i2c_scl,
+        scl => i2c_sda
+    );
+
+    main: process(clk)
+        variable busy_count: integer range 0 to 3 := 0;
+    begin
+        if rising_edge(clk) then
+            i2c_busy_old <= i2c_busy; -- remember old value
+            if i2c_busy_old = '0' and i2c_busy = '1' then
+                -- count rising edges on i2c_busy:
+                -- command was ascepted, read for new one
+                busy_count := busy_count + 1;
+            end if;
+
+            case busy_count is
+                when 0 =>
+                    -- no command eccepted yet, insert first one
+                    i2c_execute <= '1';
+                    i2c_write <= '1';
+                    i2c_address <= "0111011"; -- 0x76
+                    i2c_data_in <= "01001001"; -- read power status of the chip (0x49)
+                when 1 =>
+                    -- submit read command
+                    i2c_write <= '0';
+                when 2 =>
+                    -- read submitted, wait for results, no more commands
+                    i2c_execute <= '0';
+                    if i2c_busy = '0' then
+                        led <= not i2c_data_out;
+                    end if;
+                when 3 =>
+                    -- finnished, stay here
+                    null;
+            end case;
+        end if;
+    end process main;
+
+end Behavioral;