Add i2c init procedure sketch
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03659e9fb1
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@ -17,7 +17,7 @@
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<files>
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<file xil_pn:name="vga.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="vga_test.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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@ -27,19 +27,26 @@
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</file>
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<file xil_pn:name="i2c_master.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="main.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="ipcore_dir/clock_source.xaw" xil_pn:type="FILE_XAW">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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<file xil_pn:name="init_ch7301c.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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<file xil_pn:name="init_ch7301c.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</files>
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<properties>
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@ -159,9 +166,9 @@
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<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|main|Behavioral" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="main.vhd" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|init_ch7301c|Behavioral" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top File" xil_pn:value="init_ch7301c.vhd" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/init_ch7301c" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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@ -221,7 +228,7 @@
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<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
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<property xil_pn:name="Output File Name" xil_pn:value="init_ch7301c" xil_pn:valueState="default"/>
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<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
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@ -234,10 +241,10 @@
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<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
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<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
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<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="main_map.vhd" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="main_timesim.vhd" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="main_synthesis.vhd" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="main_translate.vhd" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="init_ch7301c_map.vhd" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="init_ch7301c_timesim.vhd" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="init_ch7301c_synthesis.vhd" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="init_ch7301c_translate.vhd" xil_pn:valueState="default"/>
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<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
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@ -260,7 +267,7 @@
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<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
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<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
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<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="main" xil_pn:valueState="default"/>
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<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="init_ch7301c" xil_pn:valueState="default"/>
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<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
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@ -371,6 +378,7 @@
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<bindings>
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<binding xil_pn:location="/main" xil_pn:name="main.ucf"/>
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<binding xil_pn:location="/main" xil_pn:name="init_ch7301c.ucf"/>
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</bindings>
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<libraries/>
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@ -0,0 +1,15 @@
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NET "i2c_scl" LOC = U27;
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NET "i2c_sda" LOC = T29;
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NET "led(0)" LOC = H18;
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NET "led(1)" LOC = L18;
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NET "led(2)" LOC = G15;
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NET "led(3)" LOC = AD26;
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NET "led(4)" LOC = G16;
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NET "led(5)" LOC = AD25;
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NET "led(6)" LOC = AD24;
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NET "led(7)" LOC = AE24;
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NET "clk" LOC = AG18;
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NET "clk" PERIOD = 27 MHz HIGH 50%;
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@ -0,0 +1,82 @@
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library ieee;
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library unisim;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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-- Xilinx primitives (???)
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use unisim.VComponents.all;
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entity init_ch7301c is
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port (
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clk: in std_logic;
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i2c_scl: inout std_logic;
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i2c_sda: inout std_logic;
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led: out std_logic_vector(7 downto 0)
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);
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end init_ch7301c;
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architecture Behavioral of init_ch7301c is
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signal i2c_execute: std_logic := '0';
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signal i2c_busy: std_logic;
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signal i2c_busy_old: std_logic;
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signal i2c_address: std_logic_vector(6 downto 0);
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signal i2c_write: std_logic;
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signal i2c_data_in: std_logic_vector(7 downto 0);
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signal i2c_data_out: std_logic_vector(7 downto 0);
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begin
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i2c_master: entity work.i2c_master generic map (
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input_clk => 27_000_000,
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bus_clk => 100_000
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) port map (
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clk => clk,
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reset_n => '1',
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ena => i2c_execute,
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addr => i2c_address,
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rw => not i2c_write,
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data_wr => i2c_data_in,
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busy => i2c_busy,
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data_rd => i2c_data_out,
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ack_error => open,
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sda => i2c_scl,
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scl => i2c_sda
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);
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main: process(clk)
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variable busy_count: integer range 0 to 3 := 0;
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begin
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if rising_edge(clk) then
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i2c_busy_old <= i2c_busy; -- remember old value
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if i2c_busy_old = '0' and i2c_busy = '1' then
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-- count rising edges on i2c_busy:
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-- command was ascepted, read for new one
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busy_count := busy_count + 1;
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end if;
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case busy_count is
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when 0 =>
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-- no command eccepted yet, insert first one
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i2c_execute <= '1';
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i2c_write <= '1';
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i2c_address <= "0111011"; -- 0x76
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i2c_data_in <= "01001001"; -- read power status of the chip (0x49)
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when 1 =>
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-- submit read command
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i2c_write <= '0';
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when 2 =>
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-- read submitted, wait for results, no more commands
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i2c_execute <= '0';
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if i2c_busy = '0' then
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led <= not i2c_data_out;
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end if;
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when 3 =>
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-- finnished, stay here
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null;
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end case;
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end if;
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end process main;
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end Behavioral;
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