83 lines
2.4 KiB
VHDL
83 lines
2.4 KiB
VHDL
library ieee;
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library unisim;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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-- Xilinx primitives (???)
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use unisim.VComponents.all;
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entity init_ch7301c is
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port (
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clk: in std_logic;
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i2c_scl: inout std_logic;
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i2c_sda: inout std_logic;
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led: out std_logic_vector(7 downto 0)
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);
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end init_ch7301c;
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architecture Behavioral of init_ch7301c is
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signal i2c_execute: std_logic := '0';
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signal i2c_busy: std_logic;
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signal i2c_busy_old: std_logic;
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signal i2c_address: std_logic_vector(6 downto 0);
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signal i2c_write: std_logic;
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signal i2c_data_in: std_logic_vector(7 downto 0);
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signal i2c_data_out: std_logic_vector(7 downto 0);
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begin
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i2c_master: entity work.i2c_master generic map (
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input_clk => 27_000_000,
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bus_clk => 100_000
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) port map (
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clk => clk,
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reset_n => '1',
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ena => i2c_execute,
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addr => i2c_address,
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rw => not i2c_write,
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data_wr => i2c_data_in,
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busy => i2c_busy,
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data_rd => i2c_data_out,
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ack_error => open,
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sda => i2c_scl,
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scl => i2c_sda
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);
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main: process(clk)
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variable busy_count: integer range 0 to 3 := 0;
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begin
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if rising_edge(clk) then
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i2c_busy_old <= i2c_busy; -- remember old value
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if i2c_busy_old = '0' and i2c_busy = '1' then
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-- count rising edges on i2c_busy:
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-- command was ascepted, read for new one
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busy_count := busy_count + 1;
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end if;
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case busy_count is
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when 0 =>
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-- no command eccepted yet, insert first one
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i2c_execute <= '1';
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i2c_write <= '1';
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i2c_address <= "0111011"; -- 0x76
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i2c_data_in <= "01001001"; -- read power status of the chip (0x49)
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when 1 =>
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-- submit read command
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i2c_write <= '0';
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when 2 =>
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-- read submitted, wait for results, no more commands
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i2c_execute <= '0';
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if i2c_busy = '0' then
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led <= not i2c_data_out;
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end if;
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when 3 =>
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-- finnished, stay here
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null;
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end case;
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end if;
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end process main;
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end Behavioral;
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