Import existing project for displaying images through DVI on the ml507
This commit is contained in:
commit
03659e9fb1
86
.gitignore
vendored
Normal file
86
.gitignore
vendored
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@ -0,0 +1,86 @@
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||||
# intermediate build files
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||||
*.bgn
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||||
*.bit
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*.bld
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*.cmd_log
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||||
*.drc
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||||
*.ll
|
||||
*.lso
|
||||
*.msd
|
||||
*.msk
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||||
*.ncd
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||||
*.ngc
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||||
*.ngd
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||||
*.ngr
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||||
*.pad
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||||
*.par
|
||||
*.pcf
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||||
*.prj
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||||
*.ptwx
|
||||
*.rbb
|
||||
*.rbd
|
||||
*.stx
|
||||
*.syr
|
||||
*.twr
|
||||
*.twx
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||||
*.unroutes
|
||||
*.ut
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||||
*.xpi
|
||||
*.xst
|
||||
*_bitgen.xwbt
|
||||
*_envsettings.html
|
||||
*_map.map
|
||||
*_map.mrp
|
||||
*_map.ngm
|
||||
*_map.xrpt
|
||||
*_ngdbuild.xrpt
|
||||
*_pad.csv
|
||||
*_pad.txt
|
||||
*_par.xrpt
|
||||
*_summary.html
|
||||
*_summary.xml
|
||||
*_usage.xml
|
||||
*_xst.xrpt
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||||
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||||
# iMPACT generated files
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||||
_impactbatch.log
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||||
impact.xsl
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impact_impact.xwbt
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ise_impact.cmd
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||||
webtalk_impact.xml
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||||
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# Core Generator generated files
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||||
xaw2verilog.log
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# project-wide generated files
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*.gise
|
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par_usage_statistics.html
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usage_statistics_webtalk.html
|
||||
webtalk.log
|
||||
webtalk_pn.xml
|
||||
|
||||
# generated folders
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iseconfig/
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xlnx_auto_0_xdb/
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xst/
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_ngo/
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_xmsgs/
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|
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# isim
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/isim*
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/fuse*
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*.exe
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*.wdb
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xilinxsim.ini
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# log files
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*.log
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# ip cores
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/ipcore_dir/*.cgc
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/ipcore_dir/*.cgp
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/ipcore_dir/*.tcl
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/ipcore_dir/*.vhd
|
||||
/ipcore_dir/*flist.txt
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||||
/ipcore_dir/_xmsgs/
|
||||
/ipcore_dir/tmp/
|
||||
108
clock_source.vhd
Normal file
108
clock_source.vhd
Normal file
@ -0,0 +1,108 @@
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--------------------------------------------------------------------------------
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-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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||||
--------------------------------------------------------------------------------
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||||
-- ____ ____
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||||
-- / /\/ /
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||||
-- /___/ \ / Vendor: Xilinx
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||||
-- \ \ \/ Version : 14.7
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||||
-- \ \ Application : xaw2vhdl
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||||
-- / / Filename : clock_source.vhd
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||||
-- /___/ /\ Timestamp : 11/13/2017 01:32:13
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-- \ \ / \
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||||
-- \___\/\___\
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||||
--
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--Command: xaw2vhdl-intstyle /repos/master/dvi_test/ipcore_dir/clock_source.xaw -st clock_source.vhd
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||||
--Design Name: clock_source
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--Device: xc5vfx70t-ff1136-3
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||||
--
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-- Module clock_source
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-- Generated by Xilinx Architecture Wizard
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||||
-- Written for synthesis tool: XST
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||||
-- Period Jitter (unit interval) for block DCM_ADV_INST = 0.024 UI
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||||
-- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.502 ns
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||||
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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library UNISIM;
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use UNISIM.Vcomponents.ALL;
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entity clock_source is
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port ( CLKIN_IN : in std_logic;
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CLKFX_OUT : out std_logic;
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CLKIN_IBUFG_OUT : out std_logic;
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CLK0_OUT : out std_logic);
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end clock_source;
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architecture BEHAVIORAL of clock_source is
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signal CLKFB_IN : std_logic;
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signal CLKFX_BUF : std_logic;
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signal CLKIN_IBUFG : std_logic;
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signal CLK0_BUF : std_logic;
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signal GND_BIT : std_logic;
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signal GND_BUS_7 : std_logic_vector (6 downto 0);
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signal GND_BUS_16 : std_logic_vector (15 downto 0);
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begin
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GND_BIT <= '0';
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GND_BUS_7(6 downto 0) <= "0000000";
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GND_BUS_16(15 downto 0) <= "0000000000000000";
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CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
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CLK0_OUT <= CLKFB_IN;
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CLKFX_BUFG_INST : BUFG
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port map (I=>CLKFX_BUF,
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O=>CLKFX_OUT);
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CLKIN_IBUFG_INST : IBUFG
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port map (I=>CLKIN_IN,
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||||
O=>CLKIN_IBUFG);
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||||
|
||||
CLK0_BUFG_INST : BUFG
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port map (I=>CLK0_BUF,
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O=>CLKFB_IN);
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||||
|
||||
DCM_ADV_INST : DCM_ADV
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||||
generic map( CLK_FEEDBACK => "1X",
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CLKDV_DIVIDE => 2.0,
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CLKFX_DIVIDE => 25,
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CLKFX_MULTIPLY => 12,
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CLKIN_DIVIDE_BY_2 => FALSE,
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||||
CLKIN_PERIOD => 10.000,
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||||
CLKOUT_PHASE_SHIFT => "NONE",
|
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DCM_AUTOCALIBRATION => TRUE,
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||||
DCM_PERFORMANCE_MODE => "MAX_SPEED",
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||||
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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||||
DFS_FREQUENCY_MODE => "LOW",
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||||
DLL_FREQUENCY_MODE => "LOW",
|
||||
DUTY_CYCLE_CORRECTION => TRUE,
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||||
FACTORY_JF => x"F0F0",
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PHASE_SHIFT => 0,
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||||
STARTUP_WAIT => FALSE,
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||||
SIM_DEVICE => "VIRTEX5")
|
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port map (CLKFB=>CLKFB_IN,
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||||
CLKIN=>CLKIN_IBUFG,
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DADDR(6 downto 0)=>GND_BUS_7(6 downto 0),
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DCLK=>GND_BIT,
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DEN=>GND_BIT,
|
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DI(15 downto 0)=>GND_BUS_16(15 downto 0),
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DWE=>GND_BIT,
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||||
PSCLK=>GND_BIT,
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||||
PSEN=>GND_BIT,
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PSINCDEC=>GND_BIT,
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RST=>GND_BIT,
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||||
CLKDV=>open,
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CLKFX=>CLKFX_BUF,
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CLKFX180=>open,
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||||
CLK0=>CLK0_BUF,
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||||
CLK2X=>open,
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||||
CLK2X180=>open,
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||||
CLK90=>open,
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||||
CLK180=>open,
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||||
CLK270=>open,
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||||
DO=>open,
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DRDY=>open,
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||||
LOCKED=>open,
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||||
PSDONE=>open);
|
||||
|
||||
end BEHAVIORAL;
|
||||
|
||||
|
||||
387
dvi_test.xise
Normal file
387
dvi_test.xise
Normal file
@ -0,0 +1,387 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="vga.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="vga_test.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="24"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="24"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="24"/>
|
||||
</file>
|
||||
<file xil_pn:name="i2c_master.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="main.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/clock_source.xaw" xil_pn:type="FILE_XAW">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector virtex5" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Busy" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin CS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin DIn" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin RdWr" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc5vfx70t" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Virtex5" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|main|Behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="main.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to System Monitor Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="ff1136" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="main_map.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="main_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="main_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="main_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="main" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SelectMAP Abort Sequence" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/vga_test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.vga_test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.vga_test" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target UCF File Name" xil_pn:value="vga.ucf" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-200X" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events) virtex5" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|vga_test|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="dvi_test" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-11-01T00:24:55" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="FF4AF74190ED5EA6F69737FA287876A7" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings>
|
||||
<binding xil_pn:location="/main" xil_pn:name="main.ucf"/>
|
||||
</bindings>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
250
i2c_master.vhd
Normal file
250
i2c_master.vhd
Normal file
@ -0,0 +1,250 @@
|
||||
-- https://eewiki.net/pages/viewpage.action?pageId=10125324
|
||||
-- License unclear
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
--
|
||||
-- FileName: i2c_master.vhd
|
||||
-- Dependencies: none
|
||||
-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
|
||||
--
|
||||
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
|
||||
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
|
||||
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
|
||||
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
|
||||
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
|
||||
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
|
||||
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
|
||||
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
|
||||
--
|
||||
-- Version History
|
||||
-- Version 1.0 11/01/2012 Scott Larson
|
||||
-- Initial Public Release
|
||||
-- Version 2.0 06/20/2014 Scott Larson
|
||||
-- Added ability to interface with different slaves in the same transaction
|
||||
-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
|
||||
-- Corrected timing of when ack_error signal clears
|
||||
-- Version 2.1 10/21/2014 Scott Larson
|
||||
-- Replaced gated clock with clock enable
|
||||
-- Adjusted timing of SCL during start and stop conditions
|
||||
-- Version 2.2 02/05/2015 Scott Larson
|
||||
-- Corrected small SDA glitch introduced in version 2.1
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
USE ieee.std_logic_unsigned.all;
|
||||
|
||||
ENTITY i2c_master IS
|
||||
GENERIC(
|
||||
input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
|
||||
bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
|
||||
PORT(
|
||||
clk : IN STD_LOGIC; --system clock
|
||||
reset_n : IN STD_LOGIC; --active low reset
|
||||
ena : IN STD_LOGIC; --latch in command
|
||||
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
|
||||
rw : IN STD_LOGIC; --'0' is write, '1' is read
|
||||
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
|
||||
busy : OUT STD_LOGIC; --indicates transaction in progress
|
||||
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
|
||||
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
|
||||
sda : INOUT STD_LOGIC; --serial data output of i2c bus
|
||||
scl : INOUT STD_LOGIC); --serial clock output of i2c bus
|
||||
END i2c_master;
|
||||
|
||||
ARCHITECTURE logic OF i2c_master IS
|
||||
CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
|
||||
TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
|
||||
SIGNAL state : machine; --state machine
|
||||
SIGNAL data_clk : STD_LOGIC; --data clock for sda
|
||||
SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
|
||||
SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
|
||||
SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
|
||||
SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
|
||||
SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
|
||||
SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
|
||||
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
|
||||
SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
|
||||
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
|
||||
SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
|
||||
BEGIN
|
||||
|
||||
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
|
||||
PROCESS(clk, reset_n)
|
||||
VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
|
||||
BEGIN
|
||||
IF(reset_n = '0') THEN --reset asserted
|
||||
stretch <= '0';
|
||||
count := 0;
|
||||
ELSIF(clk'EVENT AND clk = '1') THEN
|
||||
data_clk_prev <= data_clk; --store previous value of data clock
|
||||
IF(count = divider*4-1) THEN --end of timing cycle
|
||||
count := 0; --reset timer
|
||||
ELSIF(stretch = '0') THEN --clock stretching from slave not detected
|
||||
count := count + 1; --continue clock generation timing
|
||||
END IF;
|
||||
CASE count IS
|
||||
WHEN 0 TO divider-1 => --first 1/4 cycle of clocking
|
||||
scl_clk <= '0';
|
||||
data_clk <= '0';
|
||||
WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking
|
||||
scl_clk <= '0';
|
||||
data_clk <= '1';
|
||||
WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
|
||||
scl_clk <= '1'; --release scl
|
||||
IF(scl = '0') THEN --detect if slave is stretching clock
|
||||
stretch <= '1';
|
||||
ELSE
|
||||
stretch <= '0';
|
||||
END IF;
|
||||
data_clk <= '1';
|
||||
WHEN OTHERS => --last 1/4 cycle of clocking
|
||||
scl_clk <= '1';
|
||||
data_clk <= '0';
|
||||
END CASE;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
--state machine and writing to sda during scl low (data_clk rising edge)
|
||||
PROCESS(clk, reset_n)
|
||||
BEGIN
|
||||
IF(reset_n = '0') THEN --reset asserted
|
||||
state <= ready; --return to initial state
|
||||
busy <= '1'; --indicate not available
|
||||
scl_ena <= '0'; --sets scl high impedance
|
||||
sda_int <= '1'; --sets sda high impedance
|
||||
ack_error <= '0'; --clear acknowledge error flag
|
||||
bit_cnt <= 7; --restarts data bit counter
|
||||
data_rd <= "00000000"; --clear data read port
|
||||
ELSIF(clk'EVENT AND clk = '1') THEN
|
||||
IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
|
||||
CASE state IS
|
||||
WHEN ready => --idle state
|
||||
IF(ena = '1') THEN --transaction requested
|
||||
busy <= '1'; --flag busy
|
||||
addr_rw <= addr & rw; --collect requested slave address and command
|
||||
data_tx <= data_wr; --collect requested data to write
|
||||
state <= start; --go to start bit
|
||||
ELSE --remain idle
|
||||
busy <= '0'; --unflag busy
|
||||
state <= ready; --remain idle
|
||||
END IF;
|
||||
WHEN start => --start bit of transaction
|
||||
busy <= '1'; --resume busy if continuous mode
|
||||
sda_int <= addr_rw(bit_cnt); --set first address bit to bus
|
||||
state <= command; --go to command
|
||||
WHEN command => --address and command byte of transaction
|
||||
IF(bit_cnt = 0) THEN --command transmit finished
|
||||
sda_int <= '1'; --release sda for slave acknowledge
|
||||
bit_cnt <= 7; --reset bit counter for "byte" states
|
||||
state <= slv_ack1; --go to slave acknowledge (command)
|
||||
ELSE --next clock cycle of command state
|
||||
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
|
||||
sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
|
||||
state <= command; --continue with command
|
||||
END IF;
|
||||
WHEN slv_ack1 => --slave acknowledge bit (command)
|
||||
IF(addr_rw(0) = '0') THEN --write command
|
||||
sda_int <= data_tx(bit_cnt); --write first bit of data
|
||||
state <= wr; --go to write byte
|
||||
ELSE --read command
|
||||
sda_int <= '1'; --release sda from incoming data
|
||||
state <= rd; --go to read byte
|
||||
END IF;
|
||||
WHEN wr => --write byte of transaction
|
||||
busy <= '1'; --resume busy if continuous mode
|
||||
IF(bit_cnt = 0) THEN --write byte transmit finished
|
||||
sda_int <= '1'; --release sda for slave acknowledge
|
||||
bit_cnt <= 7; --reset bit counter for "byte" states
|
||||
state <= slv_ack2; --go to slave acknowledge (write)
|
||||
ELSE --next clock cycle of write state
|
||||
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
|
||||
sda_int <= data_tx(bit_cnt-1); --write next bit to bus
|
||||
state <= wr; --continue writing
|
||||
END IF;
|
||||
WHEN rd => --read byte of transaction
|
||||
busy <= '1'; --resume busy if continuous mode
|
||||
IF(bit_cnt = 0) THEN --read byte receive finished
|
||||
IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
|
||||
sda_int <= '0'; --acknowledge the byte has been received
|
||||
ELSE --stopping or continuing with a write
|
||||
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
|
||||
END IF;
|
||||
bit_cnt <= 7; --reset bit counter for "byte" states
|
||||
data_rd <= data_rx; --output received data
|
||||
state <= mstr_ack; --go to master acknowledge
|
||||
ELSE --next clock cycle of read state
|
||||
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
|
||||
state <= rd; --continue reading
|
||||
END IF;
|
||||
WHEN slv_ack2 => --slave acknowledge bit (write)
|
||||
IF(ena = '1') THEN --continue transaction
|
||||
busy <= '0'; --continue is accepted
|
||||
addr_rw <= addr & rw; --collect requested slave address and command
|
||||
data_tx <= data_wr; --collect requested data to write
|
||||
IF(addr_rw = addr & rw) THEN --continue transaction with another write
|
||||
sda_int <= data_wr(bit_cnt); --write first bit of data
|
||||
state <= wr; --go to write byte
|
||||
ELSE --continue transaction with a read or new slave
|
||||
state <= start; --go to repeated start
|
||||
END IF;
|
||||
ELSE --complete transaction
|
||||
state <= stop; --go to stop bit
|
||||
END IF;
|
||||
WHEN mstr_ack => --master acknowledge bit after a read
|
||||
IF(ena = '1') THEN --continue transaction
|
||||
busy <= '0'; --continue is accepted and data received is available on bus
|
||||
addr_rw <= addr & rw; --collect requested slave address and command
|
||||
data_tx <= data_wr; --collect requested data to write
|
||||
IF(addr_rw = addr & rw) THEN --continue transaction with another read
|
||||
sda_int <= '1'; --release sda from incoming data
|
||||
state <= rd; --go to read byte
|
||||
ELSE --continue transaction with a write or new slave
|
||||
state <= start; --repeated start
|
||||
END IF;
|
||||
ELSE --complete transaction
|
||||
state <= stop; --go to stop bit
|
||||
END IF;
|
||||
WHEN stop => --stop bit of transaction
|
||||
busy <= '0'; --unflag busy
|
||||
state <= ready; --go to idle state
|
||||
END CASE;
|
||||
ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
|
||||
CASE state IS
|
||||
WHEN start =>
|
||||
IF(scl_ena = '0') THEN --starting new transaction
|
||||
scl_ena <= '1'; --enable scl output
|
||||
ack_error <= '0'; --reset acknowledge error output
|
||||
END IF;
|
||||
WHEN slv_ack1 => --receiving slave acknowledge (command)
|
||||
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
|
||||
ack_error <= '1'; --set error output if no-acknowledge
|
||||
END IF;
|
||||
WHEN rd => --receiving slave data
|
||||
data_rx(bit_cnt) <= sda; --receive current slave data bit
|
||||
WHEN slv_ack2 => --receiving slave acknowledge (write)
|
||||
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
|
||||
ack_error <= '1'; --set error output if no-acknowledge
|
||||
END IF;
|
||||
WHEN stop =>
|
||||
scl_ena <= '0'; --disable scl
|
||||
WHEN OTHERS =>
|
||||
NULL;
|
||||
END CASE;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
--set sda output
|
||||
WITH state SELECT
|
||||
sda_ena_n <= data_clk_prev WHEN start, --generate start condition
|
||||
NOT data_clk_prev WHEN stop, --generate stop condition
|
||||
sda_int WHEN OTHERS; --set to internal sda signal
|
||||
|
||||
--set scl and sda outputs
|
||||
scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
|
||||
sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
|
||||
|
||||
END logic;
|
||||
3
ipcore_dir/clock_source.xaw
Normal file
3
ipcore_dir/clock_source.xaw
Normal file
@ -0,0 +1,3 @@
|
||||
XILINX-XDB 0.1 STUB 0.1 ASCII
|
||||
XILINX-XDM V1.6e
|
||||
$8cx71=(zlzd"cnsugq+apnW}oxx"gcnpf[aou''%h`bmd_rmvvfc)ph}:7=;40/2100=7&<:9=6?9;02-456438:;>6?=4:37*2><9?-cJ=H?2:3[5>453;?:79<44958EWEO_@P:;6O]W[]LJI_XKHYHMIGAG^AOO4><I[]QSB@CY^AOOLHXMQ^N^COC149BVR\XGGFRSNBDIO]UEISB9k1J^ZTPOONZ[AEJWZ]BXNFFNF]@HN773HX\VRAALX]G@WYD88:0M_YU_NLO]ZBCZVI:=<5NRVX\KKJ^WMNYSNBD179BVR\XGGFRSIJ]_DFDAHICM8<0M_YU_NLO]ZBCZVLGE]HCOQ31?DTPRVEE@TQKDS]JJLR6?2KY[WQ@NM[\@ATXZLYNXYW_E078EWQ]WFDGURHM_DZWAWHFD880M_YU_NLO]ZOI[]UEY@?j;@PT^ZIIDPUAEYZJR^RH6UMXFFDDE^K>b:CQS_YHFESTFDZ[ES]VMZHHFFCXI<94ASUY[JHKQVXNOB@IIF]SMKU6=2KY[WQ@NM[\V@UB\VFDKDM>2:CQS_YHFEST^HZNRFGW5==FZ^PTCCBV_WCOMAYCNZUFCIKn;@QPKFYPA]B:96OXZ^AOOGSA9VET_DIAALGe?DQ]WJF@NXH[YQG253=F_SUH@FLZFU[SA4YIGLNBX<=4AVX\GIMXG\^[YYQ[YQG`?DQ]WOFD[YW_E99BS_YWI[^o7LYU_R[MPMRHGE>0NBZG4:@VBB2<KEA;46MCK1]AQCc<KEA;SO[IG^KMWQ><KEA;SB[[6:AOO4>7>2IGG?9?5:AOO7^?3JF@>U?7049@HN?7=2IGGIXl;BNH@SYCA_COI85LLJDA<>EKCOHTEC;4CMIE\==DDBLS=5>6;BNHB]YE]Ol0OAEIX^@VBBYNFZ^h7NBDFY]GMSOCMl1H@FHW_LWOPLVKQ01H@FHW_NWW1>EKC@D:=6MCKHL\@LPNLLUIUR<m;BNHMKYNJ\LL==5LLJKM[LDRNNUBB^Zi;BNHMKYNJ\LLSB[[8:AOOLHXAGi0OAEFN^RFVLICm2IGGD@PSSA\P\VB9;1H@FAZT^RKEVCX[ACMXn5LLJ]EA@BEIJA27NABMHVWAA1<K[OJXHJ:;ECG@W2<LJF@;6JLM^CGRf=CKDUJH[QFNRV27>BDEVK^XBMNLH@QEQOHF8>0HNCPPDPEKWKFFJOTABJJ3:FFJa=CMZAN[ROKJTQW57=CNZUM^H_ZEOAZ[HICM;1OEl5KLM]BJAYAP880HABPFSGRQ@HDQVGDHH<4DN68@WB^9<1OYYWPCXAOAZEHZ[OHXDAA3:FTA2=CW_KGYH64EYVFVKGKi2LJOYA]Y^HE1>@FDZO27KLPSNWQG@e<NLOONLMD_CWE=>@NFV_EEY]7;GMVPZUSZh1MCXZPUOKWWd=AG\^TZLBZE09J1>OE]OM37D@[ESLBH47<B@^_I_QFNQWW[Q_WM?1GCNEJD29OKR?<EHRT_]KJD29NL_1<EV\J@XK8;OGWSJTL<2DDBH?4O59L@AT?3FZ[C^G[Ec9SLDUBWZBBJY74PHLKEVDR[h1[ECG\GOFF@==WAG]BHYF7;QPJIQ_WM8:0\_A__QKMMVGD\@\N96^\CMI5?UUCGGO?7]]JN99SWLHDLLI87_][b:QJC@^SM[DJ@l5\IL]GASODM?1XECICEb9PPDTS]YU\MDZm;R[MGMTHFF_X=?5\YRVFIZU^FJBYCCAZS29WKU2<\[_N46[\E^@VBB?<]ZOTNXHHS49UM@Q6?2\B^YKW5c9[ERYQM[YBCC?k;YKOMK^*PMH+<#?/SUWA$5(6(HYHED=4XRV5?]beW@n:<6Vkm^ObnjtQm{ybcc??;Yfn[Hoig{\n~~g`n49X4?6Z>2Q;6<;R5:Y3>3[33hx|v>5kcl`8r`ttafd+=#>;;wjgh44<pj?}ju9?t,de5451%:wKL}=n;AB{4?@=:3;p_9m5948:3?74;j3=577?7zl:4?7<f0;1:6*7f;:g?xU3j33>6495121`=3?=k<<0h4;50;395~U3k33>6495121`=3?=19=0zY6n:182>4<?sZ>h64;5968276e>>002<:5m8783>5<321q/j779;%0;><><,;31545+2`8;a>"?k320n8>50;3;>5<7s-=269h4$02973=#9803>6*>3;0g?!7e2180(<m54:&2<?143-;?6?j4$07974=#9?09h6*>7;57?!7>281/=l474:&2b?073-8;6;>4$33925=#<h0j7)=8:c9'7`<d3-9m6:5+43854>"3?3?0(9655d9'0<<092.>=768;%71>3b<,<>1485+5485g>"203<h7);m:958 0b=<2.>j774$7392<=#>:0=i6*95;4f?!012l1/:l494:&5b?b<,>?1=6*73;43?!>?2130(<<56:&13?303-896?l4$939<g=#9l097)?k:29j04<72-=364<4$6c9<2=<a:21<7*88;;1?!1f21=07d:k:18'3=<><2.<;768;%55>=1<3`?=6=4+798:7>"0?32<7)99:958?l3d290/;5462:&43?>032c>?7>5$6:9=7=#?>03;65f4d83>!1?2080(:958698m2`=83.<477=;%54>=1<3`=o6=4+798:6>"0?32<76g8e;29 2>=1;1/;:477:9j3g<72-=364<4$659<2=<g;n1<7*88;;1?!1f21=0(?856398k63=83.<477=;:m05?6=,>215?54o2094?"0033976a<6;29 2>=1;10c>=50;&4<??532e887>5$6:9=7=<g:k1<7*88;;1?!1f21=0(?;52b9'61<3821d?o4?:%5;><4<3f?j6=4+798:6>=h=00;6)97:818 20=0>10c;l50;&4<??532e<o7>5$6:9=7=<uk>?6=4=:183!1>2?20e;950;&4<??53-=j6594;n51>5<#?102>6*8a;:4?>{e:o0;6?4?:1y'3<<5k2c=;7>5$6:9=7=#?h03;65`7383>!1?2080(:o58698yg5c29096=4?{%5:>7e<a?=1<7*88;;1?!1f21=07b9=:18'3=<>:2.<m768;:p06<72;q69=4;1:?70?153-8869;4}r1:>5<5s4?;6>64=3d937=#::08<6s|2d83>7}:=909h63=f;44?xu4k3:1>v3:0;1b?85c2?=0q~:9:1828232?=0(5>5669~w16=83;p1>j5739'<5<0:2wx884?:1y'<5<0:2wx?=4?:1y'<5<0:2wvb?o50;3xyk4e290:wp`=c;295~{i:m0;6<urn3g94?7|ug8m6=4>{|l04?6=9rwe?<4?:0y~yx{GHJq8m7:6517`f0{GHKq;qMN_{|BC
|
||||
30
main.ucf
Normal file
30
main.ucf
Normal file
@ -0,0 +1,30 @@
|
||||
|
||||
# DVI-Encoder Interface
|
||||
NET "dvi_d(0)" LOC = AB8;
|
||||
NET "dvi_d(1)" LOC = AC8;
|
||||
NET "dvi_d(2)" LOC = AN12;
|
||||
NET "dvi_d(3)" LOC = AP12;
|
||||
NET "dvi_d(4)" LOC = AA9;
|
||||
NET "dvi_d(5)" LOC = AA8;
|
||||
NET "dvi_d(6)" LOC = AM13;
|
||||
NET "dvi_d(7)" LOC = AN13;
|
||||
NET "dvi_d(8)" LOC = AA10;
|
||||
NET "dvi_d(9)" LOC = AB10;
|
||||
NET "dvi_d(10)" LOC = AP14;
|
||||
NET "dvi_d(11)" LOC = AN14;
|
||||
NET "dvi_clk_p" LOC = AL11;
|
||||
NET "dvi_clk_n" LOC = AL10;
|
||||
NET "dvi_hsync" LOC = AM12;
|
||||
NET "dvi_vsync" LOC = AM11;
|
||||
NET "dvi_de" LOC = AE8;
|
||||
NET "dvi_reset" LOC = AK6;
|
||||
|
||||
NET "clk" LOC = AH15;
|
||||
NET "clk" PERIOD = 100 MHz HIGH 50%;
|
||||
|
||||
NET "switch_center" LOC = AJ6;
|
||||
|
||||
NET "led0" LOC = H18;
|
||||
NET "led1" LOC = L18;
|
||||
NET "led2" LOC = G15;
|
||||
NET "led4" LOC = G16;
|
||||
72
main.vhd
Normal file
72
main.vhd
Normal file
@ -0,0 +1,72 @@
|
||||
library ieee;
|
||||
library unisim;
|
||||
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
-- Xilinx primitives (OBUFDS)
|
||||
use unisim.VComponents.all;
|
||||
|
||||
entity main is
|
||||
port (
|
||||
clk: in std_logic;
|
||||
|
||||
dvi_d: out std_logic_vector(11 downto 0);
|
||||
dvi_clk_p: out std_logic;
|
||||
dvi_clk_n: out std_logic;
|
||||
dvi_hsync: out std_logic;
|
||||
dvi_vsync: out std_logic;
|
||||
dvi_de: out std_logic;
|
||||
dvi_reset: out std_logic;
|
||||
|
||||
switch_center: in std_logic;
|
||||
led0: out std_logic;
|
||||
led1: out std_logic;
|
||||
led2: out std_logic;
|
||||
led4: out std_logic
|
||||
);
|
||||
end main;
|
||||
|
||||
architecture Behavioral of main is
|
||||
signal clk_vga: std_logic;
|
||||
signal pixel_rgb: std_logic_vector(23 downto 0) := "111111110000000011111111";
|
||||
signal dvi_clk: std_logic; -- connect vga_sync to dvi_clk_ds
|
||||
-- tmp
|
||||
signal hsync: std_logic;
|
||||
signal vsync: std_logic;
|
||||
signal de: std_logic;
|
||||
begin
|
||||
clock_source: entity work.clock_source port map (
|
||||
CLKIN_IN => clk,
|
||||
CLKFX_OUT => clk_vga
|
||||
);
|
||||
|
||||
dvi_clk_ds: OBUFDS
|
||||
port map(
|
||||
O => dvi_clk_p,
|
||||
OB => dvi_clk_n,
|
||||
I => clk_vga
|
||||
);
|
||||
|
||||
vga_sync: entity work.vga port map (
|
||||
clk => clk_vga,
|
||||
--x, y (static color for now)
|
||||
pixel_rgb => pixel_rgb,
|
||||
dvi_d => dvi_d,
|
||||
dvi_clk => dvi_clk,
|
||||
dvi_hsync => hsync,
|
||||
dvi_vsync => vsync,
|
||||
dvi_de => de
|
||||
);
|
||||
|
||||
dvi_hsync <= hsync;
|
||||
dvi_vsync <= vsync;
|
||||
dvi_de <= de;
|
||||
|
||||
led0 <= switch_center;
|
||||
led1 <= dvi_clk;
|
||||
led2 <= hsync;
|
||||
led4 <= vsync;
|
||||
|
||||
dvi_reset <= not switch_center;
|
||||
end Behavioral;
|
||||
80
vga.vhd
Normal file
80
vga.vhd
Normal file
@ -0,0 +1,80 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity vga is
|
||||
port(
|
||||
clk: in std_logic;
|
||||
|
||||
x, y: out std_logic_vector(9 downto 0);
|
||||
pixel_rgb: in std_logic_vector(23 downto 0);
|
||||
|
||||
dvi_d: out std_logic_vector(11 downto 0);
|
||||
dvi_clk: out std_logic;
|
||||
dvi_hsync: out std_logic;
|
||||
dvi_vsync: out std_logic;
|
||||
dvi_de: out std_logic
|
||||
);
|
||||
end vga;
|
||||
|
||||
architecture behavioral of vga is
|
||||
signal second_batch: std_logic := '0';
|
||||
signal hcount: std_logic_vector(9 downto 0) := (others => '0');
|
||||
signal vcount: std_logic_vector(9 downto 0) := (others => '0');
|
||||
signal data_enabled: std_logic;
|
||||
begin
|
||||
--dvi_clk <= clk;
|
||||
dvi_clk <= second_batch;
|
||||
dvi_de <= data_enabled;
|
||||
|
||||
data_enabled <= '1' when hcount < 640 and vcount < 480 else
|
||||
'0';
|
||||
|
||||
dvi_hsync <= '0' when 656 <= hcount and hcount <= 720 else
|
||||
'1';
|
||||
dvi_vsync <= '0' when 483 <= vcount and vcount <= 487 else
|
||||
'1';
|
||||
|
||||
x <= hcount when data_enabled = '1' and hcount < 640 else std_logic_vector(to_unsigned(639, 10));
|
||||
y <= vcount when data_enabled = '1' and vcount < 480 else std_logic_vector(to_unsigned(479, 10));
|
||||
|
||||
data_output: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if data_enabled = '1' then
|
||||
if second_batch = '0' then
|
||||
dvi_d <= pixel_rgb(11 downto 0);
|
||||
else
|
||||
dvi_d <= pixel_rgb(23 downto 12);
|
||||
end if;
|
||||
else
|
||||
dvi_d <= (others => '0');
|
||||
end if;
|
||||
|
||||
second_batch <= not second_batch;
|
||||
end if;
|
||||
end process data_output;
|
||||
|
||||
hcounter: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) and second_batch = '1' then
|
||||
if hcount < 799 then
|
||||
hcount <= hcount + 1;
|
||||
else
|
||||
hcount <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process hcounter;
|
||||
|
||||
vcounter: process(clk, hcount)
|
||||
begin
|
||||
if rising_edge(clk) and second_batch = '1' and hcount = 700 then
|
||||
if vcount < 499 then
|
||||
vcount <= vcount + 1;
|
||||
else
|
||||
vcount <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process vcounter;
|
||||
end behavioral;
|
||||
104
vga_test.vhd
Normal file
104
vga_test.vhd
Normal file
@ -0,0 +1,104 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 01:47:34 11/01/2017
|
||||
-- Design Name:
|
||||
-- Module Name: /repos/master/dvi_test/vga_test.vhd
|
||||
-- Project Name: dvi_test
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: vga
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY vga_test IS
|
||||
END vga_test;
|
||||
|
||||
ARCHITECTURE behavior OF vga_test IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT vga
|
||||
PORT(
|
||||
clk : IN std_logic;
|
||||
--x : OUT std_logic_vector(9 downto 0);
|
||||
--y : OUT std_logic_vector(9 downto 0);
|
||||
--pixel_rgb : IN std_logic_vector(23 downto 0);
|
||||
dvi_d : OUT std_logic_vector(11 downto 0);
|
||||
--dvi_clk : OUT std_logic;
|
||||
dvi_clk_p : OUT std_logic;
|
||||
dvi_clk_n : OUT std_logic;
|
||||
dvi_hsync : OUT std_logic;
|
||||
dvi_vsync : OUT std_logic;
|
||||
dvi_de : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal clk : std_logic := '0';
|
||||
--signal pixel_rgb : std_logic_vector(23 downto 0) := (others => '0');
|
||||
|
||||
--Outputs
|
||||
--signal x : std_logic_vector(9 downto 0);
|
||||
--signal y : std_logic_vector(9 downto 0);
|
||||
signal dvi_d : std_logic_vector(11 downto 0);
|
||||
--signal dvi_clk : std_logic;
|
||||
signal dvi_clk_p : std_logic;
|
||||
signal dvi_clk_n : std_logic;
|
||||
signal dvi_hsync : std_logic;
|
||||
signal dvi_vsync : std_logic;
|
||||
signal dvi_de : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
constant clk_period : time := 20834 ps;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: vga PORT MAP (
|
||||
clk => clk,
|
||||
--x => x,
|
||||
--y => y,
|
||||
--pixel_rgb => pixel_rgb,
|
||||
dvi_d => dvi_d,
|
||||
--dvi_clk => dvi_clk,
|
||||
dvi_clk_p => dvi_clk_p,
|
||||
dvi_clk_n => dvi_clk_n,
|
||||
dvi_hsync => dvi_hsync,
|
||||
dvi_vsync => dvi_vsync,
|
||||
dvi_de => dvi_de
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
clk_process :process
|
||||
begin
|
||||
clk <= '0';
|
||||
wait for clk_period/2;
|
||||
clk <= '1';
|
||||
wait for clk_period/2;
|
||||
end process;
|
||||
|
||||
--pixel_rgb <= "111111111111000000000001";
|
||||
END;
|
||||
Loading…
Reference in New Issue
Block a user