riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity

Merge pull request #11 from sifive/spi

Browse Source 
SPI errata fixes
This commit is contained in:
Yunsup Lee 2017-05-02 14:36:39 -07:00 committed by GitHub
commit fd89474621
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/devices/spi/SPIFIFO.scala
View File

@ -41,7 +41,7 @@ class SPIFIFO(c: SPIParamsBase) extends Module {
val proto = SPIProtocol.decode(io.link.fmt.proto).zipWithIndex val proto = SPIProtocol.decode(io.link.fmt.proto).zipWithIndex
val cnt_quot = Mux1H(proto.map { case (s, i) => s -> (io.ctrl.fmt.len >> i) }) val cnt_quot = Mux1H(proto.map { case (s, i) => s -> (io.ctrl.fmt.len >> i) })
val cnt_rmdr = Mux1H(proto.map { case (s, i) => s -> (io.ctrl.fmt.len(i, 0).orR) }) val cnt_rmdr = Mux1H(proto.map { case (s, i) => s -> (if (i > 0) io.ctrl.fmt.len(i-1, 0).orR else UInt(0)) })
io.link.fmt <> io.ctrl.fmt io.link.fmt <> io.ctrl.fmt
io.link.cnt := cnt_quot + cnt_rmdr io.link.cnt := cnt_quot + cnt_rmdr

2
src/main/scala/devices/spi/SPIPhysical.scala
View File

@ -82,7 +82,7 @@ class SPIPhysical(c: SPIParamsBase) extends Module {
} }
val tx = (ctrl.fmt.iodir === SPIDirection.Tx) val tx = (ctrl.fmt.iodir === SPIDirection.Tx)
val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _) val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _).init
val txen = txen_in :+ txen_in.last val txen = txen_in :+ txen_in.last
io.port.sck := sck io.port.sck := sck