From eea10f51294af8529b278ea88660037d065495b4 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Tue, 2 May 2017 12:07:37 -0700 Subject: [PATCH 1/2] spi: Fix io.port.dq(3) output enable Issue: The output enable signal for DQ[3] is not driven properly. Symptoms: Output data from master to slave is not properly transmitted in quad mode. Data received from the slave is unaffected. Workaround: When interfacing with SPI flash devices, do not use the "Quad Input/Output Fast Read" command (opcode 0xEB) while in the Extended SPI protocol. Do not use the Native Quad SPI protocol. --- src/main/scala/devices/spi/SPIPhysical.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/devices/spi/SPIPhysical.scala b/src/main/scala/devices/spi/SPIPhysical.scala index 802233d..a9ce076 100644 --- a/src/main/scala/devices/spi/SPIPhysical.scala +++ b/src/main/scala/devices/spi/SPIPhysical.scala @@ -82,7 +82,7 @@ class SPIPhysical(c: SPIParamsBase) extends Module { } val tx = (ctrl.fmt.iodir === SPIDirection.Tx) - val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _) + val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _).init val txen = txen_in :+ txen_in.last io.port.sck := sck From 75d6a7c6eac209a32ecf2fc8d1b8cfc68450107d Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Tue, 2 May 2017 12:35:34 -0700 Subject: [PATCH 2/2] spi: Fix off-by-one error in calculating cycles per data frame Issue: Configuring the frame length to certain values causes incorrect operation. Symptoms: Certain frame lengths result in the master sending one extra clock pulse. The slave device may then become desynchronized. Workaround: The following frame lengths are supported and can be used. Do not use other frame lengths. * Serial mode: 0, 2, 4, 6, 8 * Dual mode: 0, 1, 3, 5, 7, 8 * Quad mode: 0, 1, 2, 3, 5, 6, 7, 8 --- src/main/scala/devices/spi/SPIFIFO.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/devices/spi/SPIFIFO.scala b/src/main/scala/devices/spi/SPIFIFO.scala index a322a1b..5bc6e82 100644 --- a/src/main/scala/devices/spi/SPIFIFO.scala +++ b/src/main/scala/devices/spi/SPIFIFO.scala @@ -41,7 +41,7 @@ class SPIFIFO(c: SPIParamsBase) extends Module { val proto = SPIProtocol.decode(io.link.fmt.proto).zipWithIndex val cnt_quot = Mux1H(proto.map { case (s, i) => s -> (io.ctrl.fmt.len >> i) }) - val cnt_rmdr = Mux1H(proto.map { case (s, i) => s -> (io.ctrl.fmt.len(i, 0).orR) }) + val cnt_rmdr = Mux1H(proto.map { case (s, i) => s -> (if (i > 0) io.ctrl.fmt.len(i-1, 0).orR else UInt(0)) }) io.link.fmt <> io.ctrl.fmt io.link.cnt := cnt_quot + cnt_rmdr