Initial commit.
This commit is contained in:
SiFive
295
src/main/scala/devices/gpio/GPIO.scala
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295
src/main/scala/devices/gpio/GPIO.scala
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@ -0,0 +1,295 @@
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// See LICENSE for license details.
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package sifive.blocks.devices.gpio
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import Chisel._
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import config._
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import regmapper._
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import uncore.tilelink2._
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import rocketchip.PeripheryBusConfig
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import util.AsyncResetRegVec
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case class GPIOConfig(address: BigInt, width: Int)
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trait HasGPIOParameters {
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val params: Tuple2[Parameters, GPIOConfig]
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implicit val p = params._1
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val c = params._2
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}
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// YAGNI: Make the PUE, DS, and
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// these also optionally HW controllable.
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// This is the base class of things you "always"
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// want to control from a HW block.
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class GPIOCtrl extends Bundle {
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val oval = Bool()
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val oe = Bool()
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val ie = Bool()
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}
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// This is the actual IOF interface.
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// Add a valid bit to indicate whether
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// there is something actually connected
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// to this.
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class GPIOPinIOFCtrl extends GPIOCtrl {
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val valid = Bool()
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}
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// By default,
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object GPIOPinIOFCtrl {
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def apply(): GPIOPinIOFCtrl = {
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val iof = Wire(new GPIOPinIOFCtrl())
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iof.valid := Bool(false)
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iof.oval := Bool(false)
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iof.oe := Bool(false)
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iof.ie := Bool(false)
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iof
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}
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}
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// This is the control for a physical
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// Pad.
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class GPIOPinCtrl extends GPIOCtrl {
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val pue = Bool() // Pull-up Enable
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val ds = Bool() // Drive Strength
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}
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object GPIOPinCtrl {
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def apply(): GPIOPinCtrl = {
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val pin = Wire(new GPIOPinCtrl())
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pin.oval := Bool(false)
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pin.oe := Bool(false)
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pin.pue := Bool(false)
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pin.ds := Bool(false)
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pin.ie := Bool(false)
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pin
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}
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}
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// Package up the inputs and outputs
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// for the IOF
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class GPIOPinIOF extends Bundle {
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val i = new Bundle {
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val ival = Bool(INPUT)
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}
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val o = new GPIOPinIOFCtrl().asOutput
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}
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// Connect both the i and o side of the pin,
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// and drive the valid signal for the IOF.
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object GPIOPinToIOF {
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def apply (pin: GPIOPin, iof: GPIOPinIOF): Unit = {
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iof <> pin
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iof.o.valid := Bool(true)
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}
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}
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// Package up the inputs and outputs
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// for the Pin
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class GPIOPin extends Bundle {
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val i = new Bundle {
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val ival = Bool(INPUT)
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}
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val o = new GPIOPinCtrl().asOutput
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}
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// This is sort of weird because
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// the IOF end up at the RocketChipTop
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// level, and we have to do the pinmux
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// outside of RocketChipTop.
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class GPIOPortIO(c: GPIOConfig) extends Bundle {
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val pins = Vec(c.width, new GPIOPin)
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val iof_0 = Vec(c.width, new GPIOPinIOF).flip
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val iof_1 = Vec(c.width, new GPIOPinIOF).flip
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}
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// It would be better if the IOF were here and
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// we could do the pinmux inside.
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trait GPIOBundle extends Bundle with HasGPIOParameters {
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val port = new GPIOPortIO(c)
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}
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trait GPIOModule extends Module with HasGPIOParameters with HasRegMap {
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val io: GPIOBundle
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//--------------------------------------------------
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// CSR Declarations
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// -------------------------------------------------
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// SW Control only.
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val portReg = Reg(init = UInt(0, c.width))
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val oeReg = Module(new AsyncResetRegVec(c.width, 0))
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val pueReg = Module(new AsyncResetRegVec(c.width, 0))
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val dsReg = Reg(init = UInt(0, c.width))
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val ieReg = Module(new AsyncResetRegVec(c.width, 0))
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// Synchronize Input to get valueReg
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val inVal = Wire(UInt(0, width=c.width))
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inVal := Vec(io.port.pins.map(_.i.ival)).asUInt
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val inSyncReg = ShiftRegister(inVal, 3)
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val valueReg = Reg(init = UInt(0, c.width), next = inSyncReg)
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// Interrupt Configuration
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val highIeReg = Reg(init = UInt(0, c.width))
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val lowIeReg = Reg(init = UInt(0, c.width))
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val riseIeReg = Reg(init = UInt(0, c.width))
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val fallIeReg = Reg(init = UInt(0, c.width))
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val highIpReg = Reg(init = UInt(0, c.width))
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val lowIpReg = Reg(init = UInt(0, c.width))
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val riseIpReg = Reg(init = UInt(0, c.width))
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val fallIpReg = Reg(init = UInt(0, c.width))
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// HW IO Function
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val iofEnReg = Module(new AsyncResetRegVec(c.width, 0))
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val iofSelReg = Reg(init = UInt(0, c.width))
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// Invert Output
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val xorReg = Reg(init = UInt(0, c.width))
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//--------------------------------------------------
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// CSR Access Logic (most of this section is boilerplate)
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// -------------------------------------------------
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val rise = ~valueReg & inSyncReg;
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val fall = valueReg & ~inSyncReg;
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// Note that these are out of order.
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regmap(
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GPIOCtrlRegs.value -> Seq(RegField.r(c.width, valueReg)),
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GPIOCtrlRegs.output_en -> Seq(RegField.rwReg(c.width, oeReg.io)),
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GPIOCtrlRegs.rise_ie -> Seq(RegField(c.width, riseIeReg)),
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GPIOCtrlRegs.rise_ip -> Seq(RegField.w1ToClear(c.width, riseIpReg, rise)),
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GPIOCtrlRegs.fall_ie -> Seq(RegField(c.width, fallIeReg)),
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GPIOCtrlRegs.fall_ip -> Seq(RegField.w1ToClear(c.width, fallIpReg, fall)),
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GPIOCtrlRegs.high_ie -> Seq(RegField(c.width, highIeReg)),
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GPIOCtrlRegs.high_ip -> Seq(RegField.w1ToClear(c.width, highIpReg, valueReg)),
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GPIOCtrlRegs.low_ie -> Seq(RegField(c.width, lowIeReg)),
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GPIOCtrlRegs.low_ip -> Seq(RegField.w1ToClear(c.width,lowIpReg, ~valueReg)),
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GPIOCtrlRegs.port -> Seq(RegField(c.width, portReg)),
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GPIOCtrlRegs.pullup_en -> Seq(RegField.rwReg(c.width, pueReg.io)),
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GPIOCtrlRegs.iof_en -> Seq(RegField.rwReg(c.width, iofEnReg.io)),
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GPIOCtrlRegs.iof_sel -> Seq(RegField(c.width, iofSelReg)),
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GPIOCtrlRegs.drive -> Seq(RegField(c.width, dsReg)),
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GPIOCtrlRegs.input_en -> Seq(RegField.rwReg(c.width, ieReg.io)),
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GPIOCtrlRegs.out_xor -> Seq(RegField(c.width, xorReg))
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)
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//--------------------------------------------------
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// Actual Pinmux
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// -------------------------------------------------
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val swPinCtrl = Wire(Vec(c.width, new GPIOPinCtrl()))
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// This strips off the valid.
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val iof0Ctrl = Wire(Vec(c.width, new GPIOCtrl()))
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val iof1Ctrl = Wire(Vec(c.width, new GPIOCtrl()))
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val iofCtrl = Wire(Vec(c.width, new GPIOCtrl()))
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val iofPlusSwPinCtrl = Wire(Vec(c.width, new GPIOPinCtrl()))
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for (pin <- 0 until c.width) {
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// Software Pin Control
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swPinCtrl(pin).pue := pueReg.io.q(pin)
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swPinCtrl(pin).oval := portReg(pin)
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swPinCtrl(pin).oe := oeReg.io.q(pin)
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swPinCtrl(pin).ds := dsReg(pin)
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swPinCtrl(pin).ie := ieReg.io.q(pin)
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// Allow SW Override for invalid inputs.
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iof0Ctrl(pin) <> swPinCtrl(pin)
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when (io.port.iof_0(pin).o.valid) {
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iof0Ctrl(pin) <> io.port.iof_0(pin).o
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}
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iof1Ctrl(pin) <> swPinCtrl(pin)
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when (io.port.iof_1(pin).o.valid) {
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iof1Ctrl(pin) <> io.port.iof_1(pin).o
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}
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// Select IOF 0 vs. IOF 1.
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iofCtrl(pin) <> Mux(iofSelReg(pin), iof1Ctrl(pin), iof0Ctrl(pin))
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// Allow SW Override for things IOF doesn't control.
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iofPlusSwPinCtrl(pin) <> swPinCtrl(pin)
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iofPlusSwPinCtrl(pin) <> iofCtrl(pin)
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// Final XOR & Pin Control
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val pre_xor: GPIOPinCtrl = Mux(iofEnReg.io.q(pin), iofPlusSwPinCtrl(pin), swPinCtrl(pin))
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io.port.pins(pin).o := pre_xor
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io.port.pins(pin).o.oval := pre_xor.oval ^ xorReg(pin)
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// Generate Interrupts
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interrupts(pin) := (riseIpReg(pin) & riseIeReg(pin)) |
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(fallIpReg(pin) & fallIeReg(pin)) |
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(highIpReg(pin) & highIeReg(pin)) |
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(lowIpReg(pin) & lowIeReg(pin))
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// Send Value to all consumers
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io.port.iof_0(pin).i.ival := inSyncReg(pin)
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io.port.iof_1(pin).i.ival := inSyncReg(pin)
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}
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}
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object GPIOOutputPinCtrl {
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def apply( pin: GPIOPin, signal: Bool,
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pue: Bool = Bool(false),
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ds: Bool = Bool(false),
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ie: Bool = Bool(false)
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): Unit = {
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pin.o.oval := signal
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pin.o.oe := Bool(true)
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pin.o.pue := pue
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pin.o.ds := ds
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pin.o.ie := ie
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}
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def apply(pins: Vec[GPIOPin], signals: Bits,
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pue: Bool, ds: Bool, ie: Bool
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): Unit = {
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for ((signal, pin) <- (signals.toBools zip pins)) {
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apply(pin, signal, pue, ds, ie)
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}
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}
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def apply(pins: Vec[GPIOPin], signals: Bits): Unit = apply(pins, signals,
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Bool(false), Bool(false), Bool(false))
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}
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object GPIOInputPinCtrl {
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def apply (pin: GPIOPin, pue: Bool = Bool(false)): Bool = {
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pin.o.oval := Bool(false)
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pin.o.oe := Bool(false)
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pin.o.pue := pue
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pin.o.ds := Bool(false)
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pin.o.ie := Bool(true)
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pin.i.ival
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}
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def apply (pins: Vec[GPIOPin], pue: Bool): Vec[Bool] = {
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val signals = Wire(Vec.fill(pins.size)(Bool(false)))
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for ((signal, pin) <- (signals zip pins)) {
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signal := GPIOInputPinCtrl(pin, pue)
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}
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signals
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}
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def apply (pins: Vec[GPIOPin]): Vec[Bool] = apply(pins, Bool(false))
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}
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// Magic TL2 Incantation to create a TL2 Slave
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class TLGPIO(p: Parameters, c: GPIOConfig)
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extends TLRegisterRouter(c.address, interrupts = c.width, beatBytes = p(PeripheryBusConfig).beatBytes)(
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new TLRegBundle(Tuple2(p, c), _) with GPIOBundle)(
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new TLRegModule(Tuple2(p, c), _, _) with GPIOModule)
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22
src/main/scala/devices/gpio/GPIOCtrlRegs.scala
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22
src/main/scala/devices/gpio/GPIOCtrlRegs.scala
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@ -0,0 +1,22 @@
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// See LICENSE for license details.
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package sifive.blocks.devices.gpio
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object GPIOCtrlRegs {
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val value = 0x00
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val input_en = 0x04
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val output_en = 0x08
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val port = 0x0c
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val pullup_en = 0x10
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val drive = 0x14
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val rise_ie = 0x18
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val rise_ip = 0x1c
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val fall_ie = 0x20
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val fall_ip = 0x24
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val high_ie = 0x28
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val high_ip = 0x2c
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val low_ie = 0x30
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val low_ip = 0x34
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val iof_en = 0x38
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val iof_sel = 0x3c
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val out_xor = 0x40
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}
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28
src/main/scala/devices/gpio/GPIOPeriphery.scala
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28
src/main/scala/devices/gpio/GPIOPeriphery.scala
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// See LICENSE for license details.
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package sifive.blocks.devices.gpio
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import Chisel._
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import diplomacy.LazyModule
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import rocketchip.{TopNetwork,TopNetworkModule}
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import uncore.tilelink2.TLFragmenter
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trait PeripheryGPIO {
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this: TopNetwork { val gpioConfig: GPIOConfig } =>
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val gpio = LazyModule(new TLGPIO(p, gpioConfig))
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gpio.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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intBus.intnode := gpio.intnode
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}
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trait PeripheryGPIOBundle {
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this: { val gpioConfig: GPIOConfig } =>
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val gpio = new GPIOPortIO(gpioConfig)
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}
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trait PeripheryGPIOModule {
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this: TopNetworkModule {
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val gpioConfig: GPIOConfig
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val outer: PeripheryGPIO
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val io: PeripheryGPIOBundle
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} =>
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io.gpio <> outer.gpio.module.io.port
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}
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43
src/main/scala/devices/gpio/JTAG.scala
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43
src/main/scala/devices/gpio/JTAG.scala
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@ -0,0 +1,43 @@
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// See LICENSE for license details.
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package sifive.blocks.devices.gpio
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import Chisel._
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// ------------------------------------------------------------
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// SPI, UART, etc are with their
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// respective packages,
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// This file is for those that don't seem to have a good place
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// to put them otherwise.
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// ------------------------------------------------------------
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import config._
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import junctions.{JTAGIO}
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class JTAGPinsIO extends Bundle {
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val TCK = new GPIOPin()
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val TMS = new GPIOPin()
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val TDI = new GPIOPin()
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val TDO = new GPIOPin()
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val TRST_n = new GPIOPin()
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}
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class JTAGGPIOPort(drvTdo: Boolean = false)(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val jtag = new JTAGIO(drvTdo)
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val pins = new JTAGPinsIO()
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}
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io.jtag.TCK := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock
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io.jtag.TMS := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true))
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io.jtag.TDI := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true))
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io.jtag.TRST := ~GPIOInputPinCtrl(io.pins.TRST_n, pue = Bool(true))
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GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO)
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if (drvTdo) {
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io.pins.TDO.o.oe := io.jtag.DRV_TDO.get
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}
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}
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Block a user