44 lines
1.1 KiB
Scala
44 lines
1.1 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.gpio
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import Chisel._
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// ------------------------------------------------------------
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// SPI, UART, etc are with their
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// respective packages,
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// This file is for those that don't seem to have a good place
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// to put them otherwise.
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// ------------------------------------------------------------
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import config._
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import junctions.{JTAGIO}
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class JTAGPinsIO extends Bundle {
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val TCK = new GPIOPin()
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val TMS = new GPIOPin()
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val TDI = new GPIOPin()
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val TDO = new GPIOPin()
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val TRST_n = new GPIOPin()
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}
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class JTAGGPIOPort(drvTdo: Boolean = false)(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val jtag = new JTAGIO(drvTdo)
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val pins = new JTAGPinsIO()
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}
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io.jtag.TCK := GPIOInputPinCtrl(io.pins.TCK, pue = Bool(true)).asClock
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io.jtag.TMS := GPIOInputPinCtrl(io.pins.TMS, pue = Bool(true))
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io.jtag.TDI := GPIOInputPinCtrl(io.pins.TDI, pue = Bool(true))
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io.jtag.TRST := ~GPIOInputPinCtrl(io.pins.TRST_n, pue = Bool(true))
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GPIOOutputPinCtrl(io.pins.TDO, io.jtag.TDO)
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if (drvTdo) {
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io.pins.TDO.o.oe := io.jtag.DRV_TDO.get
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}
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}
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