29 lines
766 B
Scala
29 lines
766 B
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.gpio
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import Chisel._
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import diplomacy.LazyModule
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import rocketchip.{TopNetwork,TopNetworkModule}
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import uncore.tilelink2.TLFragmenter
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trait PeripheryGPIO {
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this: TopNetwork { val gpioConfig: GPIOConfig } =>
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val gpio = LazyModule(new TLGPIO(p, gpioConfig))
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gpio.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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intBus.intnode := gpio.intnode
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}
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trait PeripheryGPIOBundle {
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this: { val gpioConfig: GPIOConfig } =>
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val gpio = new GPIOPortIO(gpioConfig)
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}
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trait PeripheryGPIOModule {
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this: TopNetworkModule {
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val gpioConfig: GPIOConfig
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val outer: PeripheryGPIO
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val io: PeripheryGPIOBundle
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} =>
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io.gpio <> outer.gpio.module.io.port
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}
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