riscv/sifive-blocks
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rename l2FrontendBus as fsb

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Yunsup Lee 2017-03-24 21:38:31 -07:00 committed by Megan Wachs
parent faeb14dc5a
commit 3c2277447d
1 changed files with 1 additions and 1 deletions
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src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
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@ -13,7 +13,7 @@ import uncore.tilelink2.TLWidthWidget
trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks { trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1) val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
l2FrontendBus.node := xilinxvc707pcie.master fsb.node := xilinxvc707pcie.master
xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node) xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node) xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
intBus.intnode := xilinxvc707pcie.intnode intBus.intnode := xilinxvc707pcie.intnode