From 3c2277447dc4d7a60ad68eda7a50d81c280392e6 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Fri, 24 Mar 2017 21:38:31 -0700 Subject: [PATCH] rename l2FrontendBus as fsb --- .../devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala index f37f7f9..d64d19a 100644 --- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala +++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala @@ -13,7 +13,7 @@ import uncore.tilelink2.TLWidthWidget trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks { val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1) - l2FrontendBus.node := xilinxvc707pcie.master + fsb.node := xilinxvc707pcie.master xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node) xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node) intBus.intnode := xilinxvc707pcie.intnode