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riscv/rocket-chip
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fd3ac4653cd974e6a184e70261a029e5eed9a37c
rocket-chip/src/main/scala
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Wesley W. Terpstra 01c1886b9d Utils: cacheable only if there is a cache manager
2016-09-17 00:56:21 -07:00
..
coreplex
Rename PRCI to CoreplexLocalInterrupter
2016-09-16 14:26:34 -07:00
groundtest
Comparator: don't compare addr_beat when it's irrelevant
2016-09-15 21:28:56 -07:00
junctions
rocketchip: globals are for sissies
2016-09-15 21:28:56 -07:00
rocket
Don't route PLIC interrupts through PRCI
2016-09-14 11:01:05 -07:00
rocketchip
Utils: cacheable only if there is a cache manager
2016-09-17 00:56:21 -07:00
uncore
SRAM: optionally (default: true) executable
2016-09-17 00:19:37 -07:00
unittest
[junctions] Removes the obsoleted SMI.
2016-09-14 20:06:22 -07:00
util
move tilelink-agnostic counters from uncore to util package
2016-09-13 20:47:05 -07:00
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